【ADAS GMSL bringup 2024/4/16】

customer project background

setup: 2 cameras + 712 LinkA/B EVkit
sensor:ISX031
Ser: 717F
Des:712/718
sensor do not need trigger signal and power-up then start output video data;

bringup process with 712

1. check hardware: connect, power;
2. make sure Ser and Des work on the same Link rate 3Gbps;
3. then Link lock would be locked;
4. check Ser’s PCLKDET=1?
5. if Yes, check Des’s mapped pipeline’s vid_lock =1?
6. if No, 2 things need to check: 1.check the schematic for MIPI port between Sensor and Ser: lane number, sequence, polarity; 2.0x55F: VS/HS/DE_DET_Z is asserted?
7. if 1 item cannot meet,we can use register to match it;
8. if 2 item cannot meet, we need contact ADI to get min sync blanking especially Hblanking parameter, then change sensor register to meet the sync blanking timing;
9. check Des mapped pipeline vid_lock=1?

// GMSL-A / Serializer: MAX96717F (Pixel Mode) / Mode: 1x4 / Device Address: 0x80 / Multiple-VC Case: Single VC / Multiple-VC Pipe Sharing: N/A
// PipeZ:
// Input Stream: VC0 YUV422_8bit PortB (D-PHY)

// GMSL-B / Serializer: MAX96717F (Pixel Mode) / Mode: 1x4 / Device Address: 0x80 / Multiple-VC Case: Single VC / Multiple-VC Pipe Sharing: N/A
// PipeZ:
// Input Stream: VC0 YUV422_8bit PortB (D-PHY)

// Deserializer: MAX96712 / Mode: 2 (1x4) / Device Address: 0x52
// Pipe0:
// GMSL-A Input Stream: VC0 YUV422_8bit PortB - Output Stream: VC0 YUV422_8bit PortA (D-PHY)
// Pipe1:
// GMSL-B Input Stream: VC0 YUV422_8bit PortB - Output Stream: VC1 YUV422_8bit PortA (D-PHY)

0x04,0x52,0x04,0x0B,0x00, //  (CSI_OUT_EN): CSI output disabled

// Single Link Initialization Before Serializer Device Address Change
//0x04,0x52,0x00,0x03,0xFB, //  (GMSL Link A I2C Port 0): Disabled | (Default)  (GMSL Link B I2C Port 0): Enabled |  (GMSL Link C I2C Port 0): Disabled |  (GMSL Link D I2C Port 0): Disabled
0x00,0x01, // Warning: The actual recommended delay is 5 usec.
// GMSL-B Serializer Address Change from 0x80 to 0x82
0x04,0x52,0x00,0x06,0xF2, 
0x04,0x84,0x00,0x00,0x82, // DEV : REG0 | DEV_ADDR (DEV_ADDR): 0x41
// Link Initialization for Deserializer
0x04,0x52,0x00,0x06,0xF3, // (Default)  (LINK_EN_A): Enabled | (Default)  (LINK_EN_B): Enabled | (Default)  (LINK_EN_C): Disabled | (Default)  (LINK_EN_D): Disabled
//0x04,0x52,0x00,0x03,0xFA, //  (GMSL Link A I2C Port 0): Enabled | (Default)  (GMSL Link B I2C Port 0): Enabled | (Default)  (GMSL Link C I2C Port 0): Disabled | (Default)  (GMSL Link D I2C Port 0): Disabled
0x00,0x0F, // Warning: The actual recommended delay is 5 usec.
// Video Transmit Configuration for Serializer(s)
0x04,0x84,0x00,0x02,0x03, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
0x04,0x82,0x00,0x02,0x03, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
// Pipe to Controller Mapping Configuration
0x04,0x52,0x09,0x0B,0x07, //  (MAP_EN_L Pipe 0): 0x7
0x04,0x52,0x09,0x0C,0x00, // (Default)  (MAP_EN_H Pipe 0): 0x0
0x04,0x52,0x09,0x0D,0x1E, //  (MAP_SRC_0 Pipe 0 DT): 0x1E | (Default)  (MAP_SRC_0 Pipe 0 VC): 0x0
0x04,0x52,0x09,0x0E,0x1E, //  (MAP_DST_0 Pipe 0 DT): 0x1E | (Default)  (MAP_DST_0 Pipe 0 VC): 0x0
0x04,0x52,0x09,0x0F,0x00, // (Default)  (MAP_SRC_1 Pipe 0 DT): 0x0 | (Default)  (MAP_SRC_1 Pipe 0 VC): 0x0
0x04,0x52,0x09,0x10,0x00, // (Default)  (MAP_DST_1 Pipe 0 DT): 0x0 | (Default)  (MAP_DST_1 Pipe 0 VC): 0x0
0x04,0x52,0x09,0x11,0x01, //  (MAP_SRC_2 Pipe 0 DT): 0x1 | (Default)  (MAP_SRC_2 Pipe 0 VC): 0x0
0x04,0x52,0x09,0x12,0x01, //  (MAP_DST_2 Pipe 0 DT): 0x1 | (Default)  (MAP_DST_2 Pipe 0 VC): 0x0
0x04,0x52,0x09,0x2D,0x15, //  (MAP_DPHY_DST_0 Pipe 0): 0x1 |  (MAP_DPHY_DST_1 Pipe 0): 0x1 |  (MAP_DPHY_DST_2 Pipe 0): 0x1
0x04,0x52,0x09,0x4B,0x07, //  (MAP_EN_L Pipe 1): 0x7
0x04,0x52,0x09,0x4C,0x00, // (Default)  (MAP_EN_H Pipe 1): 0x0
0x04,0x52,0x09,0x4D,0x1E, //  (MAP_SRC_0 Pipe 1 DT): 0x1E | (Default)  (MAP_SRC_0 Pipe 1 VC): 0x0
0x04,0x52,0x09,0x4E,0x5E, //  (MAP_DST_0 Pipe 1 DT): 0x1E |  (MAP_DST_0 Pipe 1 VC): 0x1
0x04,0x52,0x09,0x4F,0x00, // (Default)  (MAP_SRC_1 Pipe 1 DT): 0x0 | (Default)  (MAP_SRC_1 Pipe 1 VC): 0x0
0x04,0x52,0x09,0x50,0x40, // (Default)  (MAP_DST_1 Pipe 1 DT): 0x0 |  (MAP_DST_1 Pipe 1 VC): 0x1
0x04,0x52,0x09,0x51,0x01, //  (MAP_SRC_2 Pipe 1 DT): 0x1 | (Default)  (MAP_SRC_2 Pipe 1 VC): 0x0
0x04,0x52,0x09,0x52,0x41, //  (MAP_DST_2 Pipe 1 DT): 0x1 |  (MAP_DST_2 Pipe 1 VC): 0x1
0x04,0x52,0x09,0x6D,0x15, //  (MAP_DPHY_DST_0 Pipe 1): 0x1 |  (MAP_DPHY_DST_1 Pipe 1): 0x1 |  (MAP_DPHY_DST_2 Pipe 1): 0x1
// Double Mode Configuration
// MIPI DPHY Configuration
0x04,0x52,0x08,0xA0,0x04, // (Default)  (Port Configuration): 2 (1x4)
0x04,0x52,0x09,0x4A,0xC0, // (Default)  (Port A - Lane Count): 4
0x04,0x52,0x08,0xA3,0xE4, //  (Lane Map - PHY0 D0): Lane 0 |  (Lane Map - PHY0 D1): Lane 1 |  (Lane Map - PHY1 D0): Lane 2 |  (Lane Map - PHY1 D1): Lane 3
0x04,0x52,0x08,0xA5,0x00, // (Default)  (Polarity - PHY0 Lane 0): Normal | (Default)  (Polarity - PHY0 Lane 1): Normal | (Default)  (Polarity - PHY1 Lane 0): Normal | (Default)  (Polarity - PHY1 Lane 1): Normal | (Default)  (Polarity - PHY1 Clock Lane): Normal
0x04,0x52,0x1D,0x00,0xF4, //  (config_soft_rst_n - PHY1): 0x0
// This is to set predefined (coarse) CSI output frequency

//-------------- Frame Sync --------------/
// This example uses the Frame Sync. Make sure image sensors accept sync signals.	
// Turn off auto master link selection
0x04,0x52,0x04,0xA2,0x00,
0x00,0x0A,	 
// Disable overlap window
0x04,0x52,0x04,0xAA,0x00,
0x04,0x52,0x04,0xAB,0x00,
// AUTO_FS_LINKS = 1, FS_USE_XTAL = 1, FS_LINK_[3:0] = 0
0x04,0x52,0x04,0xAF,0xCF,	
// set FSYNC period to 25M/30 CLK cycles.
0x04,0x52,0x04,0xA7,0x0C,	//set trigger frame as 30Hz
0x04,0x52,0x04,0xA6,0xB7,
0x04,0x52,0x04,0xA5,0x35, 
// FSYNC TX ID is 8
0x04,0x52,0x04,0xB1,0x40,	//pls check the trigger pin of MAX96717F 
// Manual frame sync, output on MFP2
0x04,0x52,0x04,0xA0,0x04,



// CSI Phy 1 is 1500 Mbps/lane.
0x04,0x52,0x1D,0x00,0xF4, // (Default) 
0x04,0x52,0x04,0x18,0x38, // (Default) 
0x04,0x52,0x1D,0x00,0xF5, //  | (Default)  (config_soft_rst_n - PHY1): 0x1
0x04,0x52,0x08,0xA2,0x34, //  (phy_Stdby_2): Put PHY2 in standby mode |  (phy_Stdby_3): Put PHY3 in standby mode
0x04,0x52,0x04,0x0B,0x02, //  (CSI_OUT_EN): CSI output enabled
// Video Transmit Configuration for Serializer(s)
0x04,0x84,0x00,0x02,0x43, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled
0x04,0x82,0x00,0x02,0x43, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled

The 2 cameras’ resolution, DT, FPS are all right shown in MIPI analyzer.