发一个FPGA串口显示的小工具

最新推荐文章于 2024-10-08 15:34:29 发布

2202_75442154

最新推荐文章于 2024-10-08 15:34:29 发布

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文章标签： fpga开发单片机 stm32

本文链接：https://blog.csdn.net/2202_75442154/article/details/142128490

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直接上代码


 

#include "stdio.h" 

static   FILE*fp ;     
int init_log_file(char*fn  )
{
    fp=fopen(fn,"wb"); 

    if(fp==NULL)return-1 ;
    return 1 ;
}

int release_log_file()
{
    fclose(fp);
    return 1 ;
}



int add_to_log_file(char*str)
{ 
    fprintf(fp,"%s\n",str);
    return 1 ;
}
 




// RS-232 example
// Compiles with Microsoft Visual C++ 5.0/6.0
// verion 42390034371
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006

#include <windows.h>
#include <stdio.h>
#include <conio.h>
#include <time.h>


HANDLE hCom;

void OpenCom(unsigned int port ,unsigned int baud )
{
	static   char b[10];
	DCB dcb;
	COMMTIMEOUTS ct;
	printf("%d\n",__LINE__ );
	if (port >= 10 ) sprintf(b,"\\\\.\\COM%d",port);else 	sprintf(b,"COM%d",port);
	 printf("%d\n",__LINE__ );
	hCom = CreateFile(b, GENERIC_READ | GENERIC_WRITE, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
	printf("%d\n",__LINE__ );
	if(hCom==INVALID_HANDLE_VALUE) exit(1);
	printf("%d\n",__LINE__ );
	if(!SetupComm(hCom, 4096, 4096)) exit(1);
	printf("%d\n",__LINE__ );
	if(!GetCommState(hCom, &dcb)) exit(1);
	printf("%d\n",__LINE__ );
	dcb.BaudRate = baud ;
	((unsigned int *)(&dcb))[2] = 0x1001;  // set port properties for TXDI + no flow-control
	dcb.ByteSize = 8;
	dcb.Parity = NOPARITY;
	dcb.StopBits = 2;
	if(!SetCommState(hCom, &dcb)) exit(1);	// set the timeouts to 0
	ct.ReadIntervalTimeout = MAXDWORD ;
	ct.ReadTotalTimeoutMultiplier = 0;
	ct.ReadTotalTimeoutConstant = 0;
	ct.WriteTotalTimeoutMultiplier = 0;
	ct.WriteTotalTimeoutConstant = 0;
	if(!SetCommTimeouts(hCom, &ct)) exit(1);
	printf("ok to open %s with %d \n",b,baud  );
}

void CloseCom()
{
	CloseHandle(hCom);
}

unsigned int  WriteCom(unsigned char* buf, int len)
{
	unsigned int  nSend;
	if(!WriteFile(hCom, buf, len, &nSend, NULL)) exit(1);
	return nSend;
} 

void WriteComChar(unsigned char b)
{
	WriteCom(&b, 1);
}

unsigned char  ReadCom(unsigned char *buf, int len)
{
	unsigned char  nRec;
	if(!ReadFile(hCom, buf, len, &nRec, NULL)) exit(1);
	return (unsigned char )nRec;
}

unsigned char ReadComChar()
{
	unsigned int  nRec;	char c;  
	do {
			if(!ReadFile(hCom, &c, 1, &nRec, NULL)) exit(1);
		 
	}
	while (nRec==0    ) ; 
	return   c  ;
}

unsigned char ReadComCharTimeOut(int * msec)
{
	int de ;
	int start = clock();
	int end =start + *msec ;*msec=0;
	unsigned int  nRec;	char c;  
	do {
			if(!ReadFile(hCom, &c, 1, &nRec, NULL)) exit(1);
		    if (end <= clock()){ *msec = -1 ; break;}
	}
	while (nRec==0    ) ; 
	return   c  ;
}
 
 unsigned int get_com_u32 (){
 unsigned int r ;
 unsigned char a[4];
 a[3]	=   ReadComChar() ; 
 a[2]	=   ReadComChar() ; 
 a[1]	=   ReadComChar() ; 
 a[0]	=   ReadComChar() ; 
 r  = a[3]; r<<=8;
 r |= a[2]; r<<=8;
 r |= a[1]; r<<=8;
 r |= a[0];
 return r ; 
 }
 
 
 
int check_start (){
	unsigned char c ;
	int st = 0 ;
	while(1){	
	c = ReadComChar() ; 
	printf("%0x",c);
	if (st==0) if (c == 0x55) st=1;   else {st=0;continue ;}
	else if (st==1) if (c == 0xaa) st=2;   else {st=0;continue ;}
	else if (st==2) if (c == 0x5a) st=3;   else {st=0;continue ;}
	else if (st==3) if (c == 0xa5) { st=4; return 1; }  else   {st=0;continue ;}
	}
}


// WriteCom

const char  cmd[] = {0x00,0x00,0x4a,0x3a ,0x2a,0x1a ,0x0a,0x5b ,0x5c,0x5d ,0x5f,0xa5 ,0xb5,0xc5 ,0xd5,0xe5  };

void dec_cmd(unsigned int d){
	const char s[1024] ; 
	unsigned 	int value , addr , w1r0 ,bytes,t  ;
	w1r0 =  (d &  (0x8000<<16 ) ) ? 1: 0;
	t = (d >> 28)  & 7 ;	 	bytes = t + 1; 
	t = (d>>16) & 0X3FF ;	addr = t & 0x3ff ;
	t=(d>>8)&0xff;   value = t ;  
		 
		sprintf(s,"wr1rd=%2d bytes=%2d addr= %02X value=%02x ",w1r0,bytes,addr,value);
		printf ("%s",s);
	add_to_log_file(s);
}




main (){
	unsigned int r ,line ;
	//	init_log_file("ise.txt" ) ;
			init_log_file("vvd.txt" ) ;
	printf("enter COMM NO. ==>");
//	scanf("%d",&r);
r=54;
	OpenCom(r,115200 ) ;
   /// WriteCom(cmd ,  16 ); 
	check_start();
	while(1) {
		r = get_com_u32() ;
		if ( r==0x55aa5aa5 ) {line=0;printf("\n\n\n");}
		printf("%-20u  0X%08X   ", r,r ); 
	//	if (line==1) dec_cmd( r );
		printf("\n");		
		
		line+=1;
	}	
}

 


module la (
input clk , rst , 
output TxD ,
output reg  OF ,
input wr , RxD, 
input [31:0]  i0,i1,i2,i3,i4,i5,i6,i7 
);

parameter ClkFrequency = 100*1000*1000;	// 100MHz
parameter Baud = 115200;
parameter AW = 5 ;

function [7:0]   byte3  ;input [31:0] in ; begin byte3=in[8*3+7:8*3+0]; end  endfunction 
function [7:0]   byte2  ;input [31:0] in ; begin byte2=in[8*2+7:8*2+0]; end  endfunction 
function [7:0]   byte1  ;input [31:0] in ; begin byte1=in[8*1+7:8*1+0]; end  endfunction 
function [7:0]   byte0  ;input [31:0] in ; begin byte0=in[8*0+7:8*0+0]; end  endfunction 

wire [255:0] in256 = { i0,i1,i2,i3,i4,i5,i6,i7 } ;
wire [255:0] out256 ;
reg [255:0]  reg256 ;
  
 
wire [7:0]  RxD_data ;
 
 la_async_receiver  #(.ClkFrequency(ClkFrequency),.Baud(Baud))async_receiver(
.clk( clk ),
.RxD( RxD ),
.RxD_data_ready(RxD_data_ready ),
.RxD_data( RxD_data ) 
);


wire rd_fifo ; 
la_SC_256_fifo#(.AW(AW))  SC_256_fifo(
.clk(clk),
.rst(rst),
.din( in256 ),
.wr( wr & (~full ) & ( ~OF ) ),
.full( full ),
.dout(out256),
.rd(rd_fifo),
.empty(empty ) 
);

wire clr_OF = RxD_data_ready ;

reg [7:0]  st ;

always @ (posedge clk )   if (rst | clr_OF)  OF <=0 ; else if (full) OF<=1;
 

wire[7:0] reg8 = reg256[255:255-7] ;

reg [7:0] TxD_data ;
reg [5:0] cntr ; 
reg TxD_start ;
 wire TxD_busy ;
la_async_transmitter #(.ClkFrequency(ClkFrequency),.Baud(Baud))async_transmitter(
	 .clk(clk),
	 .TxD_start(TxD_start),
	 .TxD_data(TxD_data),
	 .TxD(TxD),
	 .TxD_busy(TxD_busy)
);
wire tx_ready = ~TxD_busy ;




always @ (posedge clk)  if (rst )  st<=0; else case (st)
0  :  begin TxD_start<=0; st<=10;  end 
10 :  begin TxD_start<=0; if (empty==0)  st<=11;end 
11 :  st<=12;
12 :  begin cntr <=0;  st<=20; reg256<= out256;end 


20 :  begin TxD_start<=0 ; if (cntr == 32) st <=100;else st<=21;end 
21 :  begin TxD_data <= reg8 ; TxD_start<= tx_ready ; if (tx_ready) st<=st+1 ;end // sent via uart 
22 :  begin TxD_start<=0;  reg256 <= {reg256[255-8:0],8'h00} ; cntr <=cntr+1 ;st<=st+1 ; end
23 :  begin if (tx_ready) st<=20;  end 

100 : st<=10; 
default st<=0;

endcase 

assign rd_fifo = st==11 ;

endmodule 




/*
module SC_256_fifo#(
.AW(4),
.DW(32)
)(

.clk(),
.rst(),

.din(),
.wr(),
.full(),

.dout(),
.rd(),
.empty(),


.fwft_dout(),
.fifo_cntr() 

);
*/

module  la_SC_256_fifo # (
        parameter AW = 5 ,
        parameter DW = 32 * 8 ,
        parameter ALMOST_FULL = 10 ,
        parameter ALMOST_EMPTY = 12
    )(
        input clk,rst,
        input [ DW-1:0] din,
        input wr,rd,
        output full,empty,
        output reg  almost_full,
        output reg almost_empty,
        output  reg  [ DW-1:0] dout,
        output   [ DW-1:0] fwft_dout,
        output reg [ AW:0] fifo_cntr
    );
    parameter MAX_FIFO_LEN = (1<<AW ) ;
    parameter ALMOST_FULL_LEN  = MAX_FIFO_LEN - 10  ;
    parameter ALMOST_EMPTY_LEN = 5  ;
    reg [ DW-1:0] buff[0:  MAX_FIFO_LEN -1] ;
    reg [ AW-1:0] wr_ptr, rd_ptr ;
    assign full  = fifo_cntr == (  MAX_FIFO_LEN   - 2) ;
    assign empty = fifo_cntr == 0 ;
    always @* almost_full <= fifo_cntr > ALMOST_FULL_LEN ;
    always @* almost_empty <= fifo_cntr < ALMOST_EMPTY_LEN ;
//    wire valid_rd =  (~empty) & rd ;
//    wire valid_wr =   (~full) & wr ;
    wire valid_rd =   rd ;
    wire valid_wr =   wr ;

    always@(posedge clk) if (rst) wr_ptr <= 0;else if(valid_wr)wr_ptr<=wr_ptr+1;
    always@(posedge clk) if (rst)rd_ptr <= 0 ;else if (valid_rd)rd_ptr <= rd_ptr+1;
    always@(posedge clk)
    casex ({rst,valid_wr,valid_rd})
        3'b1xx : fifo_cntr<=0;
        3'b010 : fifo_cntr<=fifo_cntr+1;
        3'b001 : fifo_cntr<=fifo_cntr-1;
        3'b011 ,3'b000 :fifo_cntr<=fifo_cntr ;
    endcase
    always@(posedge clk) if (valid_wr) buff[wr_ptr] <=din ;
    always@(posedge clk) if (valid_rd) dout <= buff[rd_ptr] ;
    assign  fwft_dout = buff[rd_ptr] ;
endmodule

 

module pos_det (input clk,sig,output reg pos);
reg [1:0]r ;always @ (posedge clk ) r [1:0] <= { r[0] , sig }  ; 
always @ (posedge clk ) pos <= r[1:0] == 2'b01 ;
endmodule 







///

// RS-232 RX and TX module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016

// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)

//`define SIMULATION   // in this mode, TX outputs one bit per clock cycle
                       // and RX receives one bit per clock cycle (for fast simulations)


module la_async_transmitter(
	input clk,
	input TxD_start,
	input [7:0] TxD_data,
	output TxD,
	output TxD_busy
);

// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent

parameter ClkFrequency = 25000000;	// 25MHz
parameter Baud = 115200;

//generate
//	if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
//endgenerate


`ifdef SIMULATION
wire BitTick = 1'b1;  // output one bit per clock cycle
`else
wire BitTick;
la_BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif

reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;

reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
	if(TxD_ready & TxD_start)
		TxD_shift <= TxD_data;
	else
	if(TxD_state[3] & BitTick)
		TxD_shift <= (TxD_shift >> 1);

	case(TxD_state)
		4'b0000: if(TxD_start) TxD_state <= 4'b0100;
		4'b0100: if(BitTick) TxD_state <= 4'b1000;  // start bit
		4'b1000: if(BitTick) TxD_state <= 4'b1001;  // bit 0
		4'b1001: if(BitTick) TxD_state <= 4'b1010;  // bit 1
		4'b1010: if(BitTick) TxD_state <= 4'b1011;  // bit 2
		4'b1011: if(BitTick) TxD_state <= 4'b1100;  // bit 3
		4'b1100: if(BitTick) TxD_state <= 4'b1101;  // bit 4
		4'b1101: if(BitTick) TxD_state <= 4'b1110;  // bit 5
		4'b1110: if(BitTick) TxD_state <= 4'b1111;  // bit 6
		4'b1111: if(BitTick) TxD_state <= 4'b0010;  // bit 7
		4'b0010: if(BitTick) TxD_state <= 4'b0011;  // stop1
		4'b0011: if(BitTick) TxD_state <= 4'b0000;  // stop2
		default: if(BitTick) TxD_state <= 4'b0000;
	endcase
end

assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);  // put together the start, data and stop bits
endmodule



module la_async_receiver(
	input clk,
	input RxD,
	output reg RxD_data_ready = 0,
	output reg [7:0] RxD_data = 0,  // data received, valid only (for one clock cycle) when RxD_data_ready is asserted

	// We also detect if a gap occurs in the received stream of characters
	// That can be useful if multiple characters are sent in burst
	//  so that multiple characters can be treated as a "packet"
	output RxD_idle,  // asserted when no data has been received for a while
	output reg RxD_endofpacket = 0  // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);

parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;

parameter Oversampling = 8;  // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception

//generate
	//if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
	//if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
//endgenerate


reg [3:0] RxD_state = 0;

`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1;  // receive one bit per clock cycle

`else
wire OversamplingTick;
la_BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));

// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};

// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;

always @(posedge clk)
if(OversamplingTick)
begin
	if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
	else 
	if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;

	if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
	else
	if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end

// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif

// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
	4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif;  // start bit found?
	4'b0001: if(sampleNow) RxD_state <= 4'b1000;  // sync start bit to sampleNow
	4'b1000: if(sampleNow) RxD_state <= 4'b1001;  // bit 0
	4'b1001: if(sampleNow) RxD_state <= 4'b1010;  // bit 1
	4'b1010: if(sampleNow) RxD_state <= 4'b1011;  // bit 2
	4'b1011: if(sampleNow) RxD_state <= 4'b1100;  // bit 3
	4'b1100: if(sampleNow) RxD_state <= 4'b1101;  // bit 4
	4'b1101: if(sampleNow) RxD_state <= 4'b1110;  // bit 5
	4'b1110: if(sampleNow) RxD_state <= 4'b1111;  // bit 6
	4'b1111: if(sampleNow) RxD_state <= 4'b0010;  // bit 7
	4'b0010: if(sampleNow) RxD_state <= 4'b0000;  // stop bit
	default: RxD_state <= 4'b0000;
endcase

always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};

//reg RxD_data_error = 0;
always @(posedge clk)
begin
	RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit);  // make sure a stop bit is received
	//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit);  // error if a stop bit is not received
end

`ifdef SIMULATION
assign RxD_idle = 0;
`else
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
`endif

endmodule


 

module la_BaudTickGen(
	input clk, enable,
	output tick  // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;

function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8;  // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth));  // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule

后续有空再发一下怎么用的说明