HDL—Verilog Language—Basics—Declaring wires

Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here.

实施以下电路。创建两条中间导线（根据需要命名），将AND和OR门连接在一起。请注意，提供NOT门的连线实际上是连线输出的，所以您不一定需要在这里声明第三条连线。

 题目描述说的很复杂，其实直接看图就可以了，把ab用与门连起来，cd用与门连起来，然后把两个的输出用或门连起来

输出的值就是一个是正的，一个是负的，用单目运算符~就可以了

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );
    assign out = (a&b)||(c&d);
    assign out_n = ~((a&b)||(c&d));
endmodule