HDL—Verilog Language—Modules:Hierarchy—Adder-subtractor

An adder-subtractor can be built from an adder by optionally negating one of the inputs, which is equivalent to inverting the input then adding 1. 

加法器可以通过任选地对一个输入取反来构造加法器-减法器，这相当于对输入取反再加1。

Build the adder-subtractor below.

You are provided with a 16-bit adder module, which you need to instantiate twice:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Use a 32-bit wide XOR gate to invert the b input whenever sub is 1.  (This can also be viewed as b[31:0] XORed with sub replicated 32 times.  See replication operator.).  Also connect the sub input to the carry-in of the adder.

我们有一个16位的加法器模块，需要实例化两次:
模块add16(输入[15:0]a，输入[15:0]b，输入cin，输出[15:0]sum，输出cout);
当sub为1时，使用32位宽异或门对b输入进行反转。(这也可以看作是b[31:0]异或，sub复制32次。参见复制操作符)。还要将子输入连接到加法器的进位。

这里实际上就是说一下加法器和减法器的相似之处，如何把加法器改成减法器。

按图连线

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire ad1_cout_ad2_cin;
    wire [31:0]sub_b;
    assign sub_b = b ^ { 32{sub} };
    add16 add16_1(.a(a[15:0]),.b(sub_b[15:0]),.cin(sub),.cout(ad1_cout_ad2_cin),.sum(sum[15:0]));
    add16 add16_2(.a(a[31:16]),.b(sub_b[31:16]),.cin(ad1_cout_ad2_cin),.cout(),.sum(sum[31:16]));
endmodule