HDL—Verilog Language—Procedures—If statement

这里开始使用一个新的语法if

always @(*) begin
    if (condition) begin
        out = x;
    end
    else begin
        out = y;
    end
end

assign out = (condition) ? x : y;

这两个语句的作用是一样的

Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement.

构建一个2对1的mux，在a和b之间进行选择。如果sel_b1和sel_b2都为true，则选择b。否则，选择a。执行相同的操作两次，一次使用assign语句，另一次使用过程性if语句。

sel_b1	sel_b2	out_assign out_always
0	0	a
0	1	a
1	0	a
1	1	b

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   );
    assign out_assign = ((sel_b1 == 1)&&(sel_b2 == 1)) ? b : a;
    always@(*)begin
        if((sel_b1 == 1)&&(sel_b2 == 1))
            out_always <= b;
        else
            out_always <= a;
    end
endmodule