这个主要是说明if条件满足了,就进到if语句中去。
那如果没满足条件,会怎么样呢?
会保持if条件满足的语句中
这边例程给了一个错误代码
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
endalways @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
endendmodule
当cpu_overheated的时候,就shut_off_computer
但没写else语句,当不满足的时候,shut_off_computer会保持不变仍然为1
arrive也是,当没到达的时候,gas_tank_empty也不是空的时候,就keep_driving
但没写else,后面if条件满足时就让keep_driving和gas_tank_empty值相反
不满足时,keep_driving保持不变
显然是错的
这个例程只要把if后面的else加上就可以了。
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //always @(*) begin
if (cpu_overheated == 1)
shut_off_computer = 1;
else
shut_off_computer = 0;
endalways @(*) begin
if ((arrived == 0) && (gas_tank_empty == 0))
keep_driving = 1;
else
keep_driving = 0;
endendmodule