HDL—Verilog Language—Procedures—Case statement

这一部分主要就是运用case语句

always @(*) begin     // This is a combinational circuit
    case (in)
      1'b1: begin 
               out = 1'b1;  // begin-end if >1 statement
            end
      1'b0: out = 1'b0;
      default: out = 1'bx;
    endcase
end

学会case语句的用法就可以

Case statements are more convenient than if statements if there are a large number of cases.  So, in this exercise, create a 6-to-1 multiplexer.  When sel is between 0 and 5, choose the corresponding data input.  Otherwise, output 0.  The data inputs and outputs are all 4 bits wide.

如果有大量的分支，Case语句比if语句更方便。因此，在这个练习中，创建一个6比1的多路复用器。当sel在0到5之间时，选择相应的数据输入。否则，输出0。数据输入和输出都是4位宽。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [2:0] sel,
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            3'b000:out <= data0;
            3'b001:out <= data1;
            3'b010:out <= data2;
            3'b011:out <= data3;
            3'b100:out <= data4;
            3'b101:out <= data5;
            default:out <= 4'b0000;
        endcase
    end

endmodule