EDA与VHDL题目——七人表决器

EDA与VHDL题目——七人表决器

代码

library ieee;
use ieee.std_logic_1164.all;
entity voterinseven is
port( vote:in std_logic_vector(6 downto 0);
       pass:out std_logic );
end;
architecture voter of voterinseven is
begin
	process (vote)
	variable cont:integer range 0 to 7;
	begin
		cont:=0;
		for i in 6 downto 0 loop   -- 使用FOR循环遍历7个引脚
		if vote(i)='1' then        -- 等于 1 时加一
			cont:=cont+1;
		end if;
		end loop;
		if cont>3 then
			pass<='1';
		else
			pass<='0';
		end if;
	end process;
end voter;