Quartus II 实现7人投票表决器

期末裸考系列之实现7人投票表决器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m7x1 is
port (A : in  std_logic_vector(6 downto 0);
		B : out std_logic);
end entity m7x1;
architecture one of m7x1 is
begin 
process(A)  
variable q1:std_logic_vector(2 downto 0);
begin
	q1 := "000";
	for i in 0 to  6 loop
	IF (A(i) = '1') then
		q1 := q1+1;
	end if;
	end loop;
	if(q1 > "011") then
		B <= '1';
	else B <= '0';
	end if;
	end process;
end one;