HDLBits-verilog刷题

Vectors

Four-input gates

module top_module(  
input [3:0] in,  
output out_and,  
output out_or,  
output out_xor  
);  
assign out_and = ∈  
assign out_or = |in;  
assign out_xor = ^in;  
  
endmodule  

Vector concatenation operator

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    // assign { ... } = { ... };
    assign {w,x,y,z} = {a,b,c,d,e,f,2'b11};

endmodule

Vector reversal 1

Given an 8-bit input vector [7:0], reverse its bit ordering.

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};

endmodule```