20210123 张大佳MCU VHDL常用语法 ---- Port map and OPEN

VHDL常用语法 ---- Port map and OPEN

FPGA---基本功 日常记录 备忘

Two ways to map the PORTS of a COMPONENT during its instantiation:

1　第一种 变量和引脚关联方式　Positional mapping, ports x and y correspond to a and b, respectively.

COMPONENT inverter IS
    PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 
END COMPONENT; 
... 

U1 : inverter PORT MAP (X,Y);

2　第二种 变量和引脚关联方式　 Nominal mapping would be the following:

U1: inverter PORT MAP (x => a, y => b);

  Positional mapping is easier to write, but nominal mapping is less error-prone.

 3　第三种 变量和引脚关联方式 可以有---open关键词　Ports can also be left unconnected (using the keyword OPEN). 

U2: my_circuit PORT MAP (X => a, y => b, z => OPEN);

4　　如何按位置位  =>  used to assign values to individual vector or with keyword others

signal Data_Bus : std_logic_vector (15 downto 0);
... ...

-- 1st way
Data_Bus <= (15 | 7 downto 0 => '1', others => '0');

-- 2nd way
Data_Bus (15 | 7 downto 0) <= '1';
Data_Bus (14 downto 8) <= '0';

 

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