断言Assertion:一种嵌入设计的检查,如果被检查的属性(Property)不是我们所期望的表现,那么期望序列的故障会生成错误提示。
断言目的:减少调试时间,提高验证透明度及可观测性
断言位置 1,嵌入到 RTL代码中,综合时被忽略
module fan();
rtl代码
SVA断言
endmodule
2,在设计模型中,在独立的非代码块中以及设计模型外,在设计文件中。
断言类型:即时断言和并发断言
即时断言:在当前时刻断定信号的数值情况,立即求值和时序无关,且必须放在过程块中,如task,function和always块等
即时断言格式为:
name:assert(expression) pass_statemwnt
else fail_staement
并发断言:在多个时钟周期断定序列顺序,时钟沿根据调用变量的采样值计算表达式,变量采样在预备阶段完成,表达式计算在观察阶段完成;可以放在过程块,module,interface,program中
并发断言格式为:
name:assert property (property_specification) ;
下面是实操练习
module simple_seq;
`define true 1
logic clk;
logic a, b, c, d, e;
integer i;
initial begin
clk = 1'b0;
for(i=0; i<20; i++) begin
a = $random();
b = $random();
c = $random();
d = $random();
e = $random();
@(posedge clk);
end
repeat(2) @(posedge clk);
$finish();
end
initial begin
forever clk = #25 ~clk;
a_ia: assert (a && b); // 立即断言,a=1,b=1时候success↑,其他↓fail
end
// a_s1 Simple sequence
a_s1: assert property(@(posedge clk) a);//当clk上升,a=1success,a=0 fail报警
// a_s2 simple sequence using $rose
a_s2: assert property(@(posedge clk) $rose(a));
// a_s3 simple seuence using logical operators
a_s3: assert property(@(posedge clk) a || b);//当clk上升,a=0和b=0时,断言失败
// a_cc concurrent assertion
a_cc: assert property(@(posedge clk) not (a && b));//当clk上升,a=0和b=0时,断言失败
// overlapped implcation
a_p8: assert property(@(posedge clk) a |-> b);//a“开始发生”,同时,b事件发生则↑
// non-overlapped implication
a_p9: assert property(@(posedge clk) a |=> b);
// implication using fixed time window
a_p10: assert property(@(posedge clk) a |-> ##2 b);
// implication using fixed timing and antecedent
a_p11: assert property(@(posedge clk) ((a&&b) ##1 c) |-> ##2 !d);
// timing window in SVA
a_p12: assert property(@(posedge clk) (a && b) |-> ##[1:3] c);
// Overlapping fixed time window
a_p13: assert property(@(posedge clk) (a && b) |-> ##[0:2] c);
// indefinite time window
a_p14: assert property(@(posedge clk) a |-> ##[1:$] b ##[0:$] c);
// using length operator to control the sequence length
a_p35: assert property(@(posedge clk) 1[*2:5] intersect (a ##[1:$] b ##[1:$] c));
// using select operator
a_p17: assert property(@(posedge clk) c ? d == a : d == b);
//$past construct
a_p19: assert property(@(posedge clk) (c&&d) |-> ($past((a&&b),2) == 1'b1));
// using the SVA ended construct
sequence s15a; @(posedge clk) a ##1 b; endsequence
sequence s15b; @(posedge clk) c ##1 d; endsequence
property p15a; @(posedge clk) s15a |=> s15b; endproperty
property p15b; @(posedge clk) s15a.ended |-> ##2 s15b.ended; endproperty
a15a: assert property(p15a);
a15b: assert property(p15b);
// part of property 16, passing parameter
generic_chk #(.delay(2)) i1 (a, b, clk);
generic_chk i2 (c, d, clk);
// using the `true operator
sequence s18a; @(posedge clk) a ##1 b; endsequence
sequence s18a_ext; @(posedge clk) a ##1 b ##1 `true; endsequence
sequence s18b; @(posedge clk) c ##1 d; endsequence
property p18; @(posedge clk) s18a.ended |-> ##2 s18b.ended; endproperty
property p18_ext; @(posedge clk) s18a_ext.ended |=> s18b.ended; endproperty
a18: assert property(p18);
a18_ext: assert property(p18_ext);
initial begin
$vcdpluson();
end
endmodule
module generic_chk (input logic a, b, clk);
parameter delay = 1;
// SVA using parameters
property p16;
@(posedge clk) a |-> ##delay b;
endproperty
a16: assert property(p16);
endmodule
schematic
DVE打开波形
放大图