算术逻辑单元(ALU)是指中央处理器CPU的一部分,用以计算机指令集中的执行算术与逻辑操作。某些处理器中,将ALU切分为两部分,即算术单元(AU)与逻辑单元(LU)。
tinyalu.v
module tinyalu
(
input [7:0] A,
input [7:0] B,
input clk,
input [2:0] op,
input reset_n,
input start,
output done,
output [15:0] result
);
parameter NO_OP = 3'b000;
parameter ADD_OP = 3'b001;
parameter AND_OP = 3'b010;
parameter XOR_OP = 3'b011;
parameter MUL_OP = 3'b100;
reg [15:0] result_tmp1;
reg [15:0] result_tmp2;
reg [15:0] result;
reg done_d1;
reg done_d2;
reg done;
always@(posedge clk)
if(!reset_n) begin
result_tmp1 <= 0;
result_tmp2 <= 0;
result <= 1;
done_d1 <= 0;
done_d2 <= 0;
done <= 0;
end
else begin
if(start) begin
casex(op)
ADD_OP:begin
result <= A+B;
done <= 1;
end
AND_OP:begin
result <= A&B;
done <= 1;
end
XOR_OP:begin
result <= A^B;
done <= 1;
end
MUL_OP:begin
result_tmp1 <= A*B;
result_tmp2 <= result_tmp1;
result <= result_tmp2;
done_d1 <= 1;
done_d2 <= done_d1;
done <= done_d2;
end
default:begin
result_tmp1 <=0;
result_tmp2 <= 0;
result <=0;
done_d1 <=0;
done_d2 <= 0;
done <= 1;
end
endcase
end
else begin
result_tmp1 <= 0;
result_tmp2 <= 0;
result <= 0;
done_d1 <= 0;
done_d2 <= 0;
done <= 0;
end
end
endmodule
结构展示
tinyalu_tb.sv
module top;
reg [7:0] A;
reg [7:0] B;
bit clk;
bit reset_n;
reg [2:0] op;
bit start;
wire done;
wire [15:0] result;
reg [15:0] test_cnt;
parameter NO_OP = 3'b000;
parameter ADD_OP = 3'b001;
parameter AND_OP = 3'b010;
parameter XOR_OP = 3'b011;
parameter MUL_OP = 3'b100;
parameter RST_OP = 3'b111;
tinyalu DUT (
.A (A),
.B (B),
.clk (clk),
.op (op),
.reset_n (reset_n),
.start (start),
.done (done),
.result (result)
);
initial begin
clk = 0;
forever begin
#10;
clk = ~clk;
end
end
initial begin : tester
test_cnt = 0;
reset_n = 1'b0;
@(negedge clk);
@(negedge clk);
reset_n = 1'b1;
start = 1'b0;
repeat (100) begin
@(posedge clk);
A = $urandom_range(0,8'b1111_1111);
B = $urandom_range(0,8'b1111_1111);
op= $urandom_range(0,3'b111);
start = 1'b1;
case (op) // handle the start signal
NO_OP: begin
@(posedge clk);
start = 1'b0;
end
RST_OP: begin
reset_n = 1'b0;
start = 1'b0;
@(posedge clk);
reset_n = 1'b1;
end
default: begin
wait(done);
start = 1'b0;
end
endcase // case (op_set)
test_cnt = test_cnt +1;
end
#100 $finish();
end : tester
initial begin
$fsdbDumpfile("tinyalu");
$fsdbDumpvars;
$vcdpluson;
end
endmodule : top
sim文件里面的Makefile文件
#############################
###User variables
#############################
TB = top
SEED = 2
DFILES = ../../tinyalu_dut/tinyalu.v
VFILES = ../tb/tinyalu_tb.sv
#############################
# Environment variables
# #############################
COMP = vcs -full64 -sverilog -timescale=1ps/1ps\
-nc -l comp.log -debug_pp +vcd+vcdpluson -fsdb\
-ntb_opts\
-debug_all\
-lca -cm line+fsm+cond+path+branch+tgl\
-sim_res=1ps
RUN = ./simv -l run.log -sml +ntb_random_seed=$(SEED)\
-lca -cm line+fsm+cond+path+branch+tgl
comp:
$(COMP) $(DFILES) $(VFILES)
run:
$(RUN)
run_gui:
$(RUN) -gui
clean:
rm -rf AN.DB DVEfiles csrc *.simv *.simv.daidir ucli.key 64
rm -rf *.log* *.vpd *.fsdb *.vdb novas* *verdi*
rm -rf tgl+branch+line
rm -rf simv*
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