奇数分频

实现一个上升沿触发的占空比不为50%的n分频信号

在实现一个下降沿触发的占空比不为50%的n分频信号(n 为奇数)

将两路信号相或

module clkn(clr,clk,clkout);
input clr;
input clk;
output clkout;

reg rise_clkn;
reg down_clkn;
reg [3:0] rCount;
reg [3:0] dCount;
parameter nData=4'd5;  //用来控制奇数分频数

/***********************************************/

always@(posedge clk or negedge clr)
begin
    if(!clr)
        begin
            rise_clkn<=1'b1;
            rCount<=4'd0;
        end
    else
        if(rCount==nData)
            begin
                rCount<=1'b1;
                rise_clkn<=~rise_clkn;
            end
        else if(rCount==((nData-1'b1)/2))
            begin
                rise_clkn<=~rise_clkn;
                rCount<=rCount+1'b1;
            end
        else
            rCount<=rCount+1'b1;
       
end

/***************************************************/

always@(negedge clk or negedge clr)
begin
    if(!clr)
        begin
            down_clkn<=1'b1;
            dCount<=4'd0;
        end
    else
        if(dCount==nData)
            begin
                dCount<=1'b1;
                down_clkn<=~down_clkn;
            end
        else if(dCount==((nData-1'b1)/2))
            begin
                down_clkn<=~down_clkn;
                dCount<=dCount+1'b1;
            end
        else
            dCount<=dCount+1'b1;
       
end

assign clkout=rise_clkn || down_clkn;
endmodule