序列检测

module sequence_detect
(
 input clk,
 input rst_n,
 
 input din_en,
 input din,
 
 output dout

);

//capture the posedge of din_en for data receive
reg din_en_r0,din_en_r1;

always@(posedge clk or negedge rst_n)
begin
 if(!rst_n)
  begin
   din_en_r0<=1'b0;
   din_en_r1<=1'b0;
  end
 else
  begin
   din_en_r0<=din_en;
   din_en_r1<=din_en_r0;
  end

end

wire din_flag=(~din_en_r1&& din_en_r0)?1'b1: 1'b0;

//******************************************************/

reg  [3:0] sequence_data;
always@(posedge clk or negedge rst_n)
begin
 if(!rst_n)
  begin
   sequence_data<=4'd0;
   dout<=0;
  end
 else if(din_flag)
  begin
   sequence_data<={sequence_data[2:0],din};
   dout<=(sequence_data==4'b1001)?1'b1:1'b0;
  end

end

endmodule