好的流水灯程序 Verilog

module stream(
    input clk,
    input reset,
    output [7:0] led
    );
    reg [31:0]count;
    reg [7:0]led;

    parameter[31:0] delay=32'd100000000; //delay 1 sec
always@(posedge clk or posedge reset)
begin
if(reset) 
count<=0;
else if(count==delay)
count<=0;
else
count<=count+1;

end
//always@(posedge clk or posedge reset)
//begin
//if(reset)
//led<=8'b0000_0001;
//else
//begin
// if(count==delay)
//    begin
//    led<=led<<1;
//    if(led==8'b0000_0000)
//        led<=8'b0000_0001;
//    end
//    else
//    led<=led;
//end
//end
//endmodule

always@(posedge clk or posedge reset)
begin
if(reset)
led<=8'b0000_0001;
else
   begin
    if(count==delay)
    led<={led[6:0],led[7]};
    else
    led<=led;
    end

end
endmodule