module shixisheng(
input clk,
output [2:0] data,
input rst
);
reg isNeg; //1 increase ;0 downto
reg [2:0]rData;
always@(posedge clk or negedge rst)
if(!rst)
begin
isNeg<=1'b1;
rData<=3'd0;
end
else
if(isNeg)
begin
if(rData==3'd3)
begin
isNeg<=~isNeg;
rData<=3'd3;
end
else
rData<=rData+1'b1;
end
else
begin
if(rData==3'd0)
begin
isNeg<=~isNeg;
rData<=3'd0;
end
else
rData<=rData-1'b1;
end
assign data=rData;
input clk,
output [2:0] data,
input rst
);
reg isNeg; //1 increase ;0 downto
reg [2:0]rData;
always@(posedge clk or negedge rst)
if(!rst)
begin
isNeg<=1'b1;
rData<=3'd0;
end
else
if(isNeg)
begin
if(rData==3'd3)
begin
isNeg<=~isNeg;
rData<=3'd3;
end
else
rData<=rData+1'b1;
end
else
begin
if(rData==3'd0)
begin
isNeg<=~isNeg;
rData<=3'd0;
end
else
rData<=rData-1'b1;
end
assign data=rData;
endmodule