在clock基础上,增加按键控制功能。
主要修改 data_gen 模块。
module data_gen
#(
parameter MAX_1S = 26'd49_999_999 ,
NINE = 4'd9 ,
FIVE = 4'd5
)(
input wire sys_clk ,
input wire sys_rst_n ,
input wire [03:00] key_in ,
output reg [19:00] data ,
output wire [05:00] point ,
output wire sign ,
output reg seg_en
);
// reg signal define
reg [03:00] key_r ;
reg setting ;
// reg signal define
reg [25:00] cnt_1s ;
reg add_flag ;
reg [03:00] sec_g ;
reg [03:00] sec_s ;
reg [03:00] min_g ;
reg [03:00] min_s ;
reg [03:00] hou_g ;
reg [03:00] hou_s ;
reg [19:00] data_time ;
// [03:00] key_r
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
key_r <= 4'b0000 ;
end else begin
key_r <= key_in ;
end
end
// setting ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
setting <= 1'b0 ;
end else begin
if(key_r[0] == 1'b1) begin
setting <= ~setting ;
end else begin
setting <= setting ;
end
end
end
// [25:00] cnt_1s ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt_1s <= 26'd0 ;
end else begin
if(setting == 1'b1) begin
cnt_1s <= cnt_1s ;
end else begin
if(cnt_1s == MAX_1S) begin
cnt_1s <= 26'd0 ;
end else begin
cnt_1s <= cnt_1s + 1'b1 ;
end
end
end
end
// add_flag ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
add_flag <= 1'b0 ;
end else begin
if(cnt_1s == ( MAX_1S - 1'b1) ) begin
add_flag <= 1'b1;
end else begin
add_flag <= 1'b0 ;
end
end
end
// [03:00] sec_g ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
sec_g <= 4'd0 ;
end else begin
if(setting == 1'b1) begin
if(key_r[1] == 1'b1) begin
if(sec_g == NINE) begin
sec_g <= 4'd0 ;
end else begin
sec_g <= sec_g + 1'b1 ;
end
end else begin
sec_g <= sec_g ;
end
end else begin
if(add_flag) begin
if(sec_g == NINE) begin
sec_g <= 4'd0 ;
end else begin
sec_g <= sec_g + 1'b1 ;
end
end else begin
sec_g <= sec_g ;
end
end
end
end
// [03:00] sec_s ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
sec_s <= 4'd0 ;
end else begin
if(setting == 1'b1) begin
if(key_r[1] == 1'b1 && sec_g == NINE) begin
if(sec_s == FIVE) begin
sec_s <= 4'd0 ;
end else begin
sec_s <= sec_s + 1'b1 ;
end
end else begin
sec_s <= sec_s ;
end
end else begin
if(add_flag && ( sec_g == NINE) ) begin
if(sec_s == FIVE) begin
sec_s <= 4'd0 ;
end else begin
sec_s <= sec_s + 1'b1 ;
end
end else begin
sec_s <= sec_s ;
end
end
end
end
// [03:00] min_g ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
min_g <= 4'b0 ;
end else begin
if(setting == 1'b1) begin
if(key_r[2] == 1'b1) begin
if(min_g == NINE) begin
min_g <= 4'b0 ;
end else begin
min_g <= min_g + 1'b1 ;
end
end else begin
min_g <= min_g ;
end
end else begin
if(add_flag && (sec_g == NINE) && (sec_s == FIVE)) begin
if(min_g == NINE) begin
min_g <= 4'd0 ;
end else begin
min_g <= min_g + 1'b1 ;
end
end else begin
min_g <= min_g ;
end
end
end
end
// [03:00] min_s ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
min_s <= 4'd0 ;
end else begin
if(setting == 1'b1) begin
if(key_r[2] == 1'b1 && min_g == NINE) begin
if(min_s == FIVE) begin
min_s <= 4'd0 ;
end else begin
min_s <= min_s + 1'b1 ;
end
end else begin
min_s <= min_s ;
end
end else begin
if(add_flag && (sec_g == NINE) && (sec_s == FIVE) && (min_g == NINE)) begin
if(min_s == FIVE) begin
min_s <= 4'd0 ;
end else begin
min_s <= min_s + 1'b1 ;
end
end else begin
min_s <= min_s ;
end
end
end
end
// [03:00] hou_g ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
hou_g <= 4'd0 ;
end else begin
if(setting == 1'b1) begin
if(key_r[3] == 1'b1) begin
if( (hou_s == 4'd2 && hou_g == 3'd3) || (hou_s != 4'd2 && hou_g == NINE) ) begin
hou_g <= 4'd0 ;
end else begin
hou_g <= hou_g + 1'b1 ;
end
end else begin
hou_g <= hou_g ;
end
end else begin
if(add_flag && (sec_g == NINE) && (sec_s == FIVE) && (min_g == NINE) && (min_s == FIVE)) begin
if( ((hou_s == 4'd2) && (hou_g == 4'd3)) || (hou_s != 4'd2) && (hou_g == NINE) ) begin
hou_g <= 4'd0 ;
end else begin
hou_g <= hou_g + 1'b1 ;
end
end else begin
hou_g <= hou_g ;
end
end
end
end
// [03:00] hou_s ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
hou_s <= 4'd0 ;
end else begin
if(setting == 1'b1) begin
if(hou_s == 4'd2) begin
if( (key_r[3] == 1'b1) && (hou_g == 4'd3) ) begin
hou_s <= 4'd0 ;
end else begin
hou_s <= hou_s ;
end
end else begin
if( (key_r[3] == 1'b1) && (hou_g == NINE) ) begin
hou_s <= hou_s + 1'b1 ;
end else begin
hou_s <= hou_s ;
end
end
end else begin
if(hou_s == 4'd2) begin
if(add_flag && (sec_g == NINE) && (sec_s == FIVE) && (min_g == NINE) && (min_s == FIVE) && (hou_g == 4'd3)) begin
hou_s <= 4'd0 ;
end else begin
hou_s <= hou_s ;
end
end else begin
if(add_flag && (sec_g == NINE) && (sec_s == FIVE) && (min_g == NINE) && (min_s == FIVE) && (hou_g == NINE)) begin
hou_s <= hou_s +1'b1 ;
end else begin
hou_s <= hou_s ;
end
end
end
end
end
// [19:00] data_time ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
data_time <= 20'd0 ;
end else begin
data_time <= sec_g + sec_s * 4'd10 + min_g * 7'd100 + min_s * 10'd1000 + hou_g * 14'd1000_0 + hou_s * 17'd1000_00 ;
end
end
// output
// data
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
data <= 20'd0 ;
end else begin
data <= data_time[19:00] ;
end
end
// point
assign point = 6'b010100 ;
// sign
assign sign = 1'b0 ;
// seg_en
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
seg_en <= 1'b0 ;
end else begin
seg_en <= 1'b1 ;
end
end
endmodule
module key_filter
#(
parameter MAX_CNT_20MS = 20'd999_999
)(
input wire sys_clk ,
input wire sys_rst_n ,
input wire [3:0] key_in ,
output reg [3:0] key_out
);
// reg signal define
reg [3:0] key_r0 ;
reg [3:0] key_r1 ;
reg nege ;
reg pose ;
reg [19:00] cnt_20ms ;
reg add_cnt_flag ;
reg flag_20ms ;
// key_r0 key_r1
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
key_r0 <= 1'b1 ;
end else begin
key_r0 <= key_in ;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
key_r1 <= 1'b1 ;
end else begin
key_r1 <= key_r0 ;
end
end
// nege
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
nege <= 1'b0 ;
end else begin
if(| (~key_r0 & key_r1)) begin
nege <= 1'b1 ;
end else begin
nege <= 1'b0 ;
end
end
end
// pose
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
pose <= 1'b0 ;
end else begin
if(| ( key_r0 & ~key_r1)) begin
pose <= 1'b1 ;
end else begin
pose <= 1'b0 ;
end
end
end
// add_cnt_flag
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
add_cnt_flag <= 1'b0 ;
end else begin
if(nege) begin
add_cnt_flag <= 1'b1 ;
end else begin
if(pose || cnt_20ms == MAX_CNT_20MS) begin
add_cnt_flag <= 1'b0 ;
end else begin
add_cnt_flag <= add_cnt_flag ;
end
end
end
end
// cnt_20ms
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt_20ms <= 20'd0 ;
end else begin
if(add_cnt_flag) begin
if(cnt_20ms == MAX_CNT_20MS) begin
cnt_20ms <= 20'd0 ;
end else begin
cnt_20ms <= cnt_20ms + 20'd1 ;
end
end else begin
cnt_20ms <= 20'd0 ;
end
end
end
// falg_20ms
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
flag_20ms <= 1'b0 ;
end else begin
if(cnt_20ms == MAX_CNT_20MS - 1'b1) begin
flag_20ms <= 1'b1 ;
end else begin
flag_20ms <= 1'b0 ;
end
end
end
// [3:0]key_out
always @(posedge sys_clk or negedge sys_rst_n) begin
// always @(*) begin // 这样的话 会综合成 数据选择器
if(~sys_rst_n) begin
key_out <= 4'b0000 ;
end else begin
if(flag_20ms) begin
key_out <= ~key_r1 ;
end else begin
key_out <= 4'b0000 ;
end
end
end
endmodule
`timescale 1ns/1ns
module test_key_filter();
reg sys_clk ;
reg sys_rst_n ;
reg [3:0] key_in ;
reg [07:00] cnt_tb ;
wire [3:0] key_out ;
reg rand_1 = 1'b1 ;
key_filter
#(
.MAX_CNT_20MS ( 50 )
)
key_filter_insert
(
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.key_in ( key_in ),
.key_out ( key_out )
);
parameter CYCLE = 20 ;
initial begin
sys_clk = 1'b1 ;
sys_rst_n <= 1'b0 ;
#( CYCLE * 2 ) ;
sys_rst_n <= 1'b1 ;
#( 210 ) ;
sys_rst_n <= 1'b0 ;
#( CYCLE * 10 ) ;
sys_rst_n <= 1'b1 ;
#( CYCLE * 1000 ) ;
$stop ;
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt_tb <= 0 ;
end else begin
if(cnt_tb == 249) begin
cnt_tb <= 0 ;
end else begin
cnt_tb <= cnt_tb + 1'b1 ;
end
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
key_in <= 1'b1 ;
end else begin
if(( 0 <= cnt_tb && cnt_tb <= 19 )||( 220 <= cnt_tb && cnt_tb <= 249 )) begin
key_in <= 4'b1111 ;
end else begin
if(( 20 <= cnt_tb && cnt_tb <= 69 )||( 170 <= cnt_tb && cnt_tb <= 219 ) ) begin
rand_1 = ($random) % 2 ;
key_in <= {2'b11,rand_1,1'b1} ;
end else begin
if(70 <= cnt_tb && cnt_tb <= 169) begin
key_in <= 4'b1101 ;
end else begin
key_in <= key_in ;
end
end
end
end
end
always #( CYCLE / 2 ) sys_clk = ~sys_clk ;
endmodule
`timescale 1ns/1ns
module test_data_gen();
reg sys_clk ;
reg sys_rst_n ;
reg [03:00] key_in ;
wire [19:00] data ;
wire [05:00] point ;
wire sign ;
wire seg_en ;
data_gen
#(
.MAX_1S ( 26'd10 ) ,
.NINE ( 4'd9 ) ,
.FIVE ( 4'd5 )
)
data_gen_insert
(
.sys_clk ( sys_clk ) ,
.sys_rst_n ( sys_rst_n ) ,
.key_in ( key_in ) ,
.data ( data ) ,
.point ( point ) ,
.sign ( sign ) ,
.seg_en ( seg_en )
);
parameter CYCLE = 20 ;
initial begin
sys_clk = 1'b1 ;
sys_rst_n <= 1'b0 ;
key_in <= 4'b0000 ;
#( CYCLE * 10 ) ;
sys_rst_n <= 1'b1 ;
#( 210 ) ;
sys_rst_n <= 1'b0 ;
#( 10 ) ;
#( CYCLE * 10 ) ;
sys_rst_n <= 1'b1 ;
#( CYCLE * 100 ) ;
key_in <= 4'b0001 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#( CYCLE * 10 ) ;
#(CYCLE * 100) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0010 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b0100 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
key_in <= 4'b1000 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#(CYCLE * 10 ) ;
#(CYCLE * 100) ;
key_in <= 4'b0001 ;
#(CYCLE) ;
key_in <= 4'b0000 ;
#( CYCLE * 100 ) ;
$stop ;
end
always #( CYCLE / 2 ) sys_clk = ~sys_clk ;
endmodule