1.上板前先波形仿真,又把读写地址的清零和保持写反了。
2.读地址要在取用数据的前一个时钟周期赋予RAM。
3.进行sobel运算以后像素矩阵的大小会发生改变!要调整VGA控制器里window的数值!
size_h = [(size_origin_h - kernel_h + 1 + padding + stride) /(stride)]
公式来自动手学深度学习!此处kernel = 3 ,size_h = 200 -3 + 1 = 198!
4.参数化设计大大减少了我的修改时间,以后所有的设计我都要参数化!
5.题外话:怎么让window里的画面也动起来呢?只要让读出RAM的深度比实际读取的数据深度更深就行了,因为后读出的数据会刷新前面读取出数据,而因为RAM深度和实际开窗需要读取的总深度不符合,就会产生移动的效果。
↑这是我只改了开窗参数没改RAM深度发现的。
sobel的大于阈值部分就是我们需要凸显的部分。
添加背景:
assign rgb = (set_sign)?((RD_DATA == black)?(backgroud_color):(RD_DATA))(backgroud_color);
module vga_ctrl #(
parameter H_Sync = 96,
parameter H_backporch = 40 ,
parameter H_left = 8 ,
parameter H_data = 640,
parameter H_right = 8 ,
parameter H_Frontporch = 8 ,
parameter H_total = H_Sync + H_backporch + H_left + H_data + H_right + H_Frontporch,
parameter H_width = $clog2(H_total),
parameter V_Sync = 2,
parameter V_backporch = 25 ,
parameter V_left = 8 ,
parameter V_data = 480,
parameter V_right = 8 ,
parameter V_Frontporch = 2 ,
parameter V_total = V_Sync + V_backporch + V_left + V_data + V_right + V_Frontporch,
parameter V_width = $clog2(V_total),
// parameter RGB_width = 24,
//ram
parameter window = 198,
parameter RAM_depth = 39204,//window^2
parameter RAM_depth_WIDTH = $clog2(RAM_depth),
//color
parameter RED = 8'b111_000_00,
parameter GRENN = 8'b000_111_00,
parameter BLUE = 8'b000_000_11
)(
input wire Sys_clk ,
input wire Rst_n ,
// input wire [RGB_width-1:0] RGB_IN ,
output wire [2:0] red_sign ,
output wire [2:0] grenn_sign ,
output wire [1:0] blue_sign ,
output reg H_Sync_sign ,
output reg V_Sync_sign ,
output wire [H_width-1:0] H_addr ,
output wire [V_width-1:0] V_addr ,
//ram
input wire WR_EN ,
input wire WR_CLK ,//sobel_clk 50mhz
input wire [7:0] WR_data
);
localparam white = 8'b111_111_11;
localparam black = 8'b000_000_00;
// reg [23:0] reg_RGB;
wire [7:0] rgb ;
reg [H_width-1:0] H_cnt ;
reg [H_width-1:0] H_cnt_move ;
reg H_full;
reg [V_width-1:0] V_cnt ;
reg [V_width-1:0] V_cnt_move ;
reg V_full;
wire Pixl_avai;
//mov
wire set_sign ;
reg x_move;//移动标志位x_axis
reg y_move;//移动标志位y_axis
//ram
reg [RAM_depth_WIDTH-1:0] RAM_WR_ADDR_CNT;
reg [RAM_depth_WIDTH-1:0] RAM_RD_ADDR_CNT;
wire [7:0] RD_DATA;
//background
reg [7:0] backgroud_color;
/
//addr
assign H_addr = (Pixl_avai)?(H_cnt - (H_Sync + H_backporch + H_left)):10'd0;
assign V_addr = (Pixl_avai)?(V_cnt - (V_Sync + V_backporch + V_left)):10'd0;
//pixl_able
assign Pixl_avai = (H_cnt > (H_Sync + H_backporch + H_left -1'b1 ))
&& (H_cnt <= (H_total- H_Frontporch - H_right -1'b1 ))
&& (V_cnt > (V_Sync + V_backporch + V_left -1'b1 ))
&& (V_cnt <= (V_total- V_Frontporch - V_right -1'b1 ));
assign {red_sign,grenn_sign,blue_sign} = (Pixl_avai) ? rgb : 8'd0;
//Sync
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
H_Sync_sign <= 1'b1;
end else if(H_cnt == H_total - 1'b1) begin
H_Sync_sign <= 1'b1;
end else if(H_cnt == H_Sync -1'b1) begin
H_Sync_sign <= 1'b0;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
V_Sync_sign <= 1'b1;
end else if((V_cnt == V_total - 1'b1) && (H_cnt == H_total - 1'b1)) begin
V_Sync_sign <= 1'b1;
end else if((V_cnt == V_Sync - 1'b1) && (H_cnt == H_total - 1'b1)) begin
V_Sync_sign <= 1'b0;
end
end
// always@(posedge Sys_clk or negedge Rst_n) begin
// if(Rst_n == 0) begin
// reg_RGB <= 0;
// end else begin
// reg_RGB <= RGB_IN;
// end
// end
//
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
backgroud_color <= white;
end else if(V_addr >= 0 && V_addr <= 159) begin
backgroud_color <= RED;
end else if(V_addr >= 160 && V_addr <= 319) begin
backgroud_color <= GRENN;
end else if(V_addr >= 320 && V_addr <= 479) begin
backgroud_color <= BLUE;
end else begin
backgroud_color <= white;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
x_move <= 0;
end else if((H_cnt_move == H_data - 1'b1 -window)
&& (V_cnt == V_total - 1'b1)
&& (H_cnt == H_total - 1'b1)) begin
x_move <= 1;
end else if((H_cnt_move == 1)
&& (V_cnt == V_total - 1'b1)
&& (H_cnt == H_total - 1'b1)) begin
x_move <= 0;
end else begin
x_move <= x_move;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
y_move <= 0;
end else if((V_cnt_move == V_data - 1'b1 - window)
&& (V_cnt == V_total - 1'b1)
&& (H_cnt == H_total - 1'b1)) begin
y_move <= 1;
end else if((V_cnt_move == 1)
&& (V_cnt == V_total - 1'b1)
&& (H_cnt == H_total - 1'b1)) begin
y_move <= 0;
end else begin
y_move <= y_move;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if (Rst_n == 0) begin
H_cnt_move <= 0;
end else if(V_full && x_move == 0) begin
H_cnt_move <= H_cnt_move + 1'b1;
end else if(V_full && x_move == 1) begin
H_cnt_move <= H_cnt_move - 1'b1;
end else begin
H_cnt_move <= H_cnt_move;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if (Rst_n == 0) begin
V_cnt_move <= 0;
end else if(V_full && y_move == 1) begin
V_cnt_move <= V_cnt_move - 1'b1;
end else if(V_full && y_move == 0) begin
V_cnt_move <= V_cnt_move + 1'b1;
end else begin
V_cnt_move <= V_cnt_move;
end
end
// always@(posedge Sys_clk or negedge Rst_n) begin
// if(Rst_n == 0) begin
// set_sign <= 0;
// end else if(Pixl_avai) begin
// if((H_addr <= H_cnt_move + window -1'b1)
// && (H_addr >= H_cnt_move)
// && (V_addr <= V_cnt_move + window -1'b1)
// && (V_addr >= V_cnt_move)) begin
// set_sign <= 1'b1;
// end else begin
// set_sign <= 0;
// end
// end else begin
// set_sign <= 0;
// end
// end
assign set_sign = (Pixl_avai)?((((H_addr <= H_cnt_move + window -1'b1)
&& (H_addr >= H_cnt_move)
&& (V_addr <= V_cnt_move + window -1'b1)
&& (V_addr >= V_cnt_move)))
?(1'b1):(1'b0))
:1'b0;
assign rgb = (set_sign)?(RD_DATA):(backgroud_color);
// assign rgb = (set_sign)?((RD_DATA == black)?(backgroud_color):(RD_DATA)):(backgroud_color);
// always@(posedge Sys_clk or negedge Rst_n) begin
// if(Rst_n == 0) begin
// rgb <= black;
// end else if(set_sign) begin
// rgb <= white;
// end else begin
// rgb <= black;
// end
// end
//assign REAL_RGB = (RD_DATA == black)?(backgroud_color):(RD_DATA);
///
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
H_cnt <= 0;
end else if(H_cnt == H_total - 1'b1) begin
H_cnt <= 0;
end else begin
H_cnt <= H_cnt + 1'b1;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
H_full <= 1'b0;
end else if(H_cnt == H_total - 1'b1) begin
H_full <= 1'b1;
end else begin
H_full <= 1'b0;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
V_cnt <= 0;
end else if((V_cnt == V_total - 1'b1) && (H_cnt == H_total - 1'b1)) begin
V_cnt <= 0;
end else if(H_cnt == H_total - 1'b1) begin
V_cnt <= V_cnt + 1'b1;
end else begin
V_cnt <= V_cnt;
end
end
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
V_full <= 1'b0;
end else if((V_cnt == V_total - 1'b1) && (H_cnt == H_total - 1'b1)) begin
V_full <= 1'b1;
end else begin
V_full <= 1'b0;
end
end
//
//RD_EN
assign RD_EN = (((H_cnt > (H_Sync + H_backporch + H_left -2'd2) + H_cnt_move))
&& ((H_cnt <= (H_Sync + H_backporch + H_left -2'd2) + H_cnt_move + window))
&& ((V_cnt > (V_Sync + V_backporch + V_left -1'b1) + V_cnt_move))
&& ((V_cnt <= (V_Sync + V_backporch + V_left -1'b1) + V_cnt_move + window)));
/
//RAM_WR_ADDR_CNT
always@(posedge WR_CLK or negedge Rst_n) begin
if(Rst_n == 0) begin
RAM_WR_ADDR_CNT <= 'd0;
end else if((RAM_WR_ADDR_CNT == RAM_depth -1'b1) && (WR_EN == 1'b1)) begin
RAM_WR_ADDR_CNT <= 'd0;
end else if(WR_EN == 1'b1) begin
RAM_WR_ADDR_CNT <= RAM_WR_ADDR_CNT + 1'b1;
end else begin
RAM_WR_ADDR_CNT <= RAM_WR_ADDR_CNT;
end
end
//RAM_RD_ADDR_CNT
always@(posedge Sys_clk or negedge Rst_n) begin
if(Rst_n == 0) begin
RAM_RD_ADDR_CNT <= 'd0;
end else if(RD_EN) begin
if(RAM_RD_ADDR_CNT == RAM_depth -1'b1) begin
RAM_RD_ADDR_CNT <= 'd0;
end else begin
RAM_RD_ADDR_CNT <= RAM_RD_ADDR_CNT + 1'b1;
end
end else begin
RAM_RD_ADDR_CNT <= RAM_RD_ADDR_CNT;
end
end
// //ILA
// wire [35:0] CONTROL0 ;
// wire [9:0] TRIG0 ;
// assign TRIG0 = {
// RAM_WR_ADDR_CNT[15:6]};
//
bram_40000x8_sw_sr INST0_bram_40000x8_sw_sr (
.clka ( WR_CLK ), // input write clk
.wea ( WR_EN ), // input [0 : 0] wr_en
.addra ( RAM_WR_ADDR_CNT ), // input [15 : 0] wr_addr
.dina ( WR_data ), // input [7 : 0] wr_addr
.clkb ( Sys_clk ), // input read clk
.addrb ( RAM_RD_ADDR_CNT ), // input [15 : 0] rd_addr
.doutb ( RD_DATA ) // output [7 : 0] rd_data
);
// cs_icon Inst0_cs_icon (
// .CONTROL0 ( CONTROL0 ) // INOUT BUS [35:0]
// );
// cs_ila Inst0_ila (
// .CONTROL ( CONTROL0 ), // INOUT BUS [35:0]
// .CLK ( WR_CLK ), // IN
// .TRIG0 ( TRIG0 ) // IN BUS [9:0]
// );
endmodule