【FPGA】FIFO的Verilog设计之同步FIFO的设计

这个同步FIFO的设计方法是调用异步读写双端口RAM来实现的。

关于异步读写双端口RAM的设计，前面博文已经讲到过了：【FPGA】双端口RAM的设计（异步读写）

此时使用双端口RAM来设计FIFO，可以使用一套端口进行写操作，一套端口进行读操作的方式来实现，例如例化方式大概是这样的：

ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH) DP_RAM (
.address_0 (wr_pointer) , // address_0 input 
.data_0    (data_in)    , // data_0 bi-directional
.cs_0      (wr_cs)      , // chip select
.we_0      (wr_en)      , // write enable
.oe_0      (1'b0)       , // output enable
.address_1 (rd_pointer) , // address_q input
.data_1    (data_ram)   , // data_1 bi-directional
.cs_1      (rd_cs)      , // chip select
.we_1      (1'b0)       , // Read enable
.oe_1      (rd_en)        // output enable
);  

这样就可以同时读写。

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其原理大概如此：

 FIFO uses a dual port memory and there will be two pointers to point read and write addresses. Here is a generalized block diagram of FIFO. 

 

Generally fifos are implementedusing rotating pointers. We can call write and read pointers of a FIFO as headand tail of data area. Initially read and write pointers of the FIFO will pointto the same location

Here is an example to explain howFIFO uses the memory. This is a fifo of length 8, WP and RP are the locationswhere write pointer and read pointer points. Shaded area in the diagram isfilled with data.