HDLBits-Edge capture register

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).对于32位矢量中的每个位，当输入信号在一个时钟周期内从1变为下一个时钟周期的0时，就可以捕获。"捕获 "意味着输出将保持1，直到寄存器被复位（同步复位）。

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.每个输出位的行为就像一个SR触发器：在1到0转换发生后的周期，输出位应该被设置（到1）。当复位为高电平时，输出位应在正的时钟边沿复位（至0）。如果上述两个事件同时发生，复位优先。在下面的示例波形的最后4个周期中，"复位 "事件比 "设置 "事件早发生一个周期，所以这里没有冲突。

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.在下面的示例波形中，复位、in[1]和out[1]又分别显示，以示清晰。

输入为32位的数据，捕获每一位的下降沿，如果检测到下降沿，输出中对应的位置高且保持直到检测到reset为高；如果某一个时钟上升沿同时检测到输入数据位的下降沿和reset为高，则reset优先，即输出为低。

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] r_in;
    always @ (posedge clk)
        begin 
            r_in <= in;
            if(reset)
                out <= 0;
            else
                for(int i = 0; i <=31; i ++)
                    begin 
                        if(~in[i] & r_in[i])
                            out[i] <= 1;
                        else
                            out[i] <= out[i];
                    end
        end            
            
endmodule