HDLBits刷题笔记 Edgecapture

1.证明：在不同的always块中，寄存器的延迟是一样的，这也是Verilog生成并行电路与C语言的编程本质的区别。

Verilog源文件 

module topmodule(
    input clk,
    //input reset,
    input [31:0] in,
    output reg [31:0] out0,
    output reg [31:0] out1,
    output reg [31:0] out2
    );
    //reg [31:0] in_last0;
    //reg [31:0] in_last1;
    //reg [31:0] in_last2;
    
    always@(posedge clk)begin
        out0<=in;
        out1<=in;
    end
    
    always@(posedge clk)begin
        out2<=in;
    end
    
endmodule

tb测试文件 

module topmodule_testbench( );
    reg clk;
    reg [31:0] in;
    wire [31:0] out0;
    wire [31:0] out1;
    wire [31:0] out2;//testbench中的信号类型定义：输入必须是reg型，输出必须是wire型
        
   topmodule topmodule(
    .clk(clk),
    .in(in),
    .out0(out0),
    .out1(out1),
    .out2(out2)
    );
    
    initial begin clk=0;end
    always begin
        #10;
        clk=~clk;
    end
    initial begin
        #500;
        in=32'h000e;
        #500;
        in=32'h0002;
        #500;
        in=32'h0003;
        #500;
        in=0;
    end
    
endmodule

仿真结果

 

2.edgecapture答案：

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    //检测下降沿
    reg [31:0] in2;
    always@(posedge clk)begin
        in2<=in;
    end
    
    always@(posedge clk)begin
        if(reset)
            out='b0;
        else begin
            //in2<=in;
            out<=(~in) & in2 |  out;//当检测到下降沿，out[i]<=1，否则out<=out;
        end
    end
    
endmodule