Verilog刷题

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最新推荐文章于 2024-04-16 16:26:01 发布

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文章标签： fpga

本文链接：https://blog.csdn.net/SMI_L_E/article/details/131681675

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该模块基于HDLBits实现了一个32位的加减器，通过使用16位加法器模块两次，以及一个32位的XOR门来根据sub输入翻转b输入，从而实现加法和减法功能。当sub为1时，相当于对b进行取反再加1的操作。输出sum为计算结果。

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HDLBits刷题–Module addsub

题目叙述

An adder-subtractor can be built from an adder by optionally negating one of the inputs, which is equivalent to inverting the input then adding 1. The net result is a circuit that can do two operations: (a + b + 0) and (a + ~b + 1). See Wikipedia if you want a more detailed explanation of how this circuit works.
Build the adder-subtractor below.
You are provided with a 16-bit adder module, which you need to instantiate twice:
module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
Use a 32-bit wide XOR gate to invert the b input whenever sub is 1. (This can also be viewed as b[31:0] XORed with sub replicated 32 times. See replication operator.). Also connect the sub input to the carry-in of the adder.
请添加图片描述

//我的解答
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire [15:0]sum1,sum2;
    wire [31:0]c;
    wire c1;
    assign c = b ^{32{sub}};
	add16 add161 ( 
        .a(a[15:0]), 
        .b(c[15:0]), 
        .cin(sub), 
        .sum(sum1), 
        .cout(c1) 
    );
    add16 add162 ( 
        .a(a[31:16]), 
        .b(c[31:16]), 
        .cin(c1), 
        .sum(sum2), 
        .cout() 
    );
    assign sum = {sum2,sum1};
endmodule