【HDLBits习题 2】Circuit - Combinational Logic（1）Basic Gates

1. Exams/m2014 q4h（Wire）

module top_module (
    input in,
    output out
);
	assign out = in;
endmodule

2. Exams/m2014 q4i（GND）

module top_module (
    output out
);
	assign out = 1'b0;
endmodule

3. Exams/m2014 q4e（NOR）

module top_module (
    input in1,
    input in2,
    output out
);
    assign out = ~(int1|int2);
endmodule

4. Exams/m2014 q4f（Anothor gate）

module top_module (
    input in1,
    input in2,
    output out
);
    assign out = int1 & (~int2);
endmodule

5.Exams/m2014 q4g （Two gates）

module top_module (
    input in1,
    input in2,
    input in3,
    output out
);
    wire w;
    
	assign out = w ^ int3;
    assign w = int1 ^~ int2;
endmodule

6. Gates（More logic gates）

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
	assign out_and   = a&b;
    assign out_or    = a|b;
    assign out_xor   = a^b;
    assign out_nand  = ~(a&b);
    assign out_nor	 = ~(a|b);
    assign out_xnor  = a^~b;
    assign out_anotb = a&(~b);
endmodule

7. 7420（7420 chip）

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y
);
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule

8. Truthtable1（Truth tables）

module top_module( 
    input x3,
    input x2,
    input x1,
    output f
);
    assign f = (~x3 & x2 & ~x1) | 
       		   (~x3 & x2 & x1)  | 
               (x3 & ~x2 & x1)  | 
        	   (x3 & x2 & x1);
endmodule

9. Mt2015 eq2（Two-bit equality）

module top_module ( 
    input [1:0] A, 
    input [1:0] B, 
    output z
); 
    assign z = (A==B);
endmodule

10. Mt2015 q4a（Simple circuit A）

module top_module (
    input x, 
    input y, 
    output z
);
    assign z = (x^y)&x;
endmodule

11. Mt2015 q4b（Simple circuit B）

module top_module ( 
    input x, 
    input y, 
    output z 
);
	assign z = x ^~ y;
endmodule

12. Mt2015 q4（Combine circuits A and B）

module top_module (
    input x, 
    input y, 
    output z
);
    wire w1, w2, w3, w4;
    
    A IA1 ( x, y, w1 );
    B IB1 ( x, y, w2 );
    A IA2 ( x, y, w3 );
    B IB2 ( x, y, w4 );
    assign z = (w1|w2) ^ (w3&w4);
endmodule

module A (
    input x, 
    input y, 
    output z
);
    assign z = (x^y)&x;
endmodule

module B ( 
    input x, 
    input y, 
    output z 
);
	assign z = x ^~ y;
endmodule

13. Ringer（Ring or vibrate?）

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,
    output motor
);
    assign ringer = ring & (~vibrate_mode);
    assign motor  = ring & vibrate_mode;
endmodule

14. Thermostat（Thermostat）

  方法1：

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
	assign heater = too_cold & mode;
    assign aircon = too_hot & (~mode);
    assign fan    = fan_on ? 1 : ((too_cold & mode) | (too_hot & (~mode)) ? 1 : 0);
endmodule

  方法2：

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
	assign heater = too_cold & mode;
    assign aircon = too_hot & (~mode);
    assign fan    = fan_on | heater | aircon;
endmodule

15. Popcount3（3-bit population count）

  方法1：

module top_module( 
    input [2:0] in,
    output reg [1:0] out
);
    always @(*) begin
		out = 2'b0;
        for (int i=0; i<3; i++) begin
            if (in[i]) begin
                out = out + 1'b1;
            end
        end
    end
endmodule

  方法2：

module top_module( 
    input [2:0] in,
    output [1:0] out
);
    assign out[0] = in[0]^in[1]^in[2];
    assign out[1] = in[2]&in[1] |
        			in[2]&in[0] |
        			in[1]&in[0];
endmodule

16. Gatesv（Gates and vectors）

  方法1：

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different
);
    assign out_both = {in[2]&in[3], in[1]&in[2], in[1]&in[0]};
    assign out_any  = {in[3]|in[2], in[2]|in[1], in[1]|in[0]};
    assign out_different = {in[3]^in[0], in[2]^in[3], in[1]^in[2], in[0]^in[1]};
endmodule

  方法2：

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different
);
    assign out_both = in[2:0] & in[3:1];
    assign out_any  = in[3:1] | in[2:0];
    assign out_different = in ^ {in[0], in[3:1]};
endmodule

17. Gatesv100（Even longer vectors）

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different
);
    assign out_both = in[98:0] & in[99:1];
    assign out_any  = in[99:1] | in[98:0];
    assign out_different = in ^ {in[0], in[99:1]};
endmodule