【verilog学习14】HDLBits：Circuit_Combinational Logic_Basic gates

I. NOR

1.代码编写

module top_module (
    input in1,
    input in2,
    output out);
    assign out=~(in1|in2);
endmodule

2.提交结果

3.题目分析

注意verilog运算符的优先级。

II. Mt2015 eq2 (Two-bit equality)

1.代码编写

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    assign z=(A==B)?1'b1:1'b0;
endmodule

2.提交结果

3.题目分析

Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

• if条件表达式里用“==”。

III. Mt2015 q4b （simple circuit B）

1.代码编写

module top_module ( input x, input y, output z );
    assign z=~(x^y);
endmodule

2.提交结果

3.题目分析

Circuit B can be described by the following simulation waveform:

这是同或的波形。

IV. Mt2015 q4 (combine circuit A and B)

1.代码编写

//===========================方法1：module===========================
module top_module (input x, input y, output z);
	wire w2,w3,w4,w5;
    IA instance1(.x(x),.y(y),.z(w2));
    IB instance2(.x(x),.y(y),.z(w3));
    IA instance3(.x(x),.y(y),.z(w4));
    IB instance4(.x(x),.y(y),.z(w5));
    assign z=(w2|w3)^(w4&w5);
endmodule
module IA (input x,input y,output z);
    assign z = (x^y) & x;
endmodule
module IB (input x,input y,output z);
    assign z=~(x^y);
endmodule
//===========================方法1：task===========================
module top_module (input x, input y, output z);
    wire w2,w3,w4,w5;
    //===task A========
    task IA;
        input x,y;
        output z;
        z = (x^y) & x; //这里的x,y,z都是reg，不可用assign
    endtask
    //===task B========
    task IB;
        input x,y;
        output z;
        z = ~(x^y); //这里的x,y,z都是reg，不可用assign
    endtask
    //===output========
    always@(*) begin
        IA(x,y,w2);
        IA(x,y,w4);
        IB(x,y,w3);
        IB(x,y,w5);
    end
        assign z=(w2|w3)^(w4&w5);
endmodule

2.提交结果

3.题目分析

Taken from 2015 midterm question 4

See mt2015_q4a and mt2015_q4b for the submodules used here. The top-level design consists of two instantiations each of subcircuits A and B, as shown below.

本题用module、task都可以。
※ 尽管类型名不同，实例的名字也不可重复。 （IA instance1存在，IB的实例就不可再用instance1）。

task的用法：注意 task那一行不能写input/output端口；在task内部不能用always/initial过程块，但是在过程块里可以用task。

task task_id;
[declaration]
procedural_statement
endtask

task的调用

task_id(端口1, 端口 2, …, 端口 N);
task_id是要调用的任务名，端口 1、端口 2，…是参数列表。参数列表给出传入任务的数据（进入任务的输入端）和接收返回结果的变量（从任务的输出端接收返回结果） 。任务调用语句中，参数列表的顺序必须与任务定义中的端口声明顺序相同。任务调用语句是过程性语句，所以任务调用中接收返回数据的变量必须是寄存器类型。

V. Ringer (Ring or Vibrate)

1.代码编写

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign ringer=(ring&~vibrate_mode)? 1'b1:1'b0;
    assign motor=(ring&vibrate_mode)? 1'b1:1'b0;
endmodule

2.提交结果

3.题目分析

hardware designers often think “The (output should be ___ ) when (inputs are ___ )”
The above problem description is written in an imperative form suitable for software programming (if ring then do this), so you must convert it to a more declarative form suitable for hardware implementation (assign ringer = ___). Being able to think in, and translate between, both styles is one of the most important skills needed for hardware design.
上面的问题描述是写成适合软件编程的命令式的（if ring then do this），所以你必须把它转换成更适合硬件实现的声明式的形式（assign ringer = ___）。 能够在两种风格之间进行思考和转换是硬件设计所需的最重要技能之一。

VI. Thermostat

1.代码编写

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    assign fan=(fan_on|heater|aircon)? 1'b1:1'b0; //when turn the fan on
    assign heater=(mode&too_cold)? 1'b1:1'b0;
    assign aircon=(~mode&too_hot)? 1'b1:1'b0;
    
endmodule

2.提交结果

3.题目分析

A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.

The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.

Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.

• 这是一个恒温器系统，看好题目条件即可。

VII. Popcount3 (3 bits population count)

1.代码编写

module top_module( 
    input [2:0] in,
    output [1:0] out );
    integer i;
    always@(*) begin
        out=2'd0; //init here
        for(i=0;i<3;i++) begin
            out=(in[i])? out+2'd1:out;
        end
    end
endmodule

2.提交结果

3.题目分析

• Initialize ‘out’ between ‘always_begin’ and ‘for’.

VIII. Gatesv (gates and vectors)

1.代码编写

//============================没必要这样写============================
module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
	integer i;
    always@(*) begin
        for(i=0;i<3;i++) begin
            out_both[i]=(in[i]&in[i+1])? 1'b1:1'b0;
            out_any[i+1]=(in[i+1]|in[i])? 1'b1:1'b0;
            out_different[i]=(in[i]^in[i+1])? 1'b1:1'b0;
        end
        out_different[3]=(in[3]^in[0])? 1'b1:1'b0;
    end
endmodule
//============================还是这样简单============================
/*The both, any, and different outputs use two-input AND, OR, and XOR operations, respectively.
 Using vectors, this can be done in 3 assign statements.*/
 module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    assign out_both=in[2:0]&in[3:1];
    assign out_any=in[3:1]|in[2:0];
    assign out_different={in[3]^in[0],in[2:0]^in[3:1]};
endmodule

2.提交结果

success

3.题目分析

You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:

out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are ‘1’. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[3].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

• 用Vector很方便。

IX. Gatesv100 (Even longer vectors)

1.代码编写

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    assign out_both=in[98:0]&in[99:1];
    assign out_any=in[99:1]|in[98:0];
    assign out_different={in[99]^in[0],in[98:0]^in[99:1]};
endmodule

2.提交结果

3.题目分析

See also the shorter version: Gates and vectors.

You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:

out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are ‘1’. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[99].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].

• 还是用Vector很方便。