输入的主密钥为 128bit, 密钥扩展运算开始后, 根据输入的主密钥每一轮产生 32bit的轮密钥, 密钥派生操作共进行 32 轮。 根据主密钥产生轮密钥的运算过程如算法说明所
示。 轮密钥可串行输出。
算法要求:
代码:
module key
(
//in
clk_sys,reset_sys_n,crypto_key, //输入,时钟、复位低有效、主密钥
key_expansion_run, //密钥扩展操作启动脉冲,高有效
//out
key_expansion_busy, //密钥扩展模块busy状态指示标志,高有效
crypto_rnd_key_vld, //密钥扩展产生的轮密钥有效指示信号
crypto_rnd_key //轮密钥信号
);
input clk_sys;
input reset_sys_n;
input [127:0]crypto_key; //主密钥
input key_expansion_run; //启动信号脉冲
output key_expansion_busy;
output crypto_rnd_key_vld;
output [31:0]crypto_rnd_key;
reg key_expansion_busy; //状态指示标志
reg key_expansion_busy_n;
reg outclk; //输出时钟
reg outclk_n;
reg crypto_rnd_key_vld; //轮密钥有效指示
reg crypto_rnd_key_vld_n;
reg [31:0]MK0; //主密钥拆分寄存器
reg [31:0]MK1;
reg [31:0]MK2;
reg [31:0]MK3;
reg [31:0]MK0_N;
reg [31:0]MK1_N;
reg [31:0]MK2_N;
reg [31:0]MK3_N;
reg [31:0]FK0 = 32'hA3B1BAC6; //FK寄存器
reg [31:0]FK1 = 32'h56AA3350;
reg [31:0]FK2 = 32'h677D9197;
reg [31:0]FK3 = 32'hB27022DC;
reg [31:0]CK [1:32];
reg [31:0] KI0; //4个K寄存器
reg [31:0] KI1;
reg [31:0] KI2;
reg [31:0] KI3;
reg [31:0] KI0_N;
reg [31:0] KI1_N;
reg [31:0] KI2_N;
reg [31:0] KI3_N;
reg [31:0] KI4;
reg [31:0] KI4_N;
reg [5:0] i; //轮密钥计数器i,记0-31
reg [5:0] i_n;
reg [3:0] timecnt; //定时器,给一个轮密钥周期用
reg [3:0] timecnt_n;
reg [31:0] A; //非线性变化输入寄存器
reg [31:0] A_N;
reg [31:0] tA; //非线性变换后tA寄存器
reg [31:0] tA_n;
reg [7:0] a0; //Sbox寄存器
reg [7:0] a1;
reg [7:0] a2;
reg [7:0] a3;
reg [7:0] a0_n; //非线性变化A拆分寄存器
reg [7:0] a1_n;
reg [7:0] a2_n;
reg [7:0] a3_n;
reg [31:0] L; //线性变化寄存器
reg [31:0] L_N;
//时序电路,初始化定时器
always @(posedge clk_sys,negedge reset_sys_n)
begin
if(!reset_sys_n)
timecnt <= 4'd0;
else
timecnt <= timecnt_n;
end
//组合电路,定时器启动
always @(*)
begin
if(timecnt < 4'd8)
timecnt_n = timecnt + 1'b1;
else if(timecnt == 4'd8)
timecnt_n = 4'd0;
else
timecnt_n = timecnt;
end
//时序电路,设置处理时钟有效信号
always @(posedge clk_sys,negedge reset_sys_n)
begin
if(!reset_sys_n)
outclk <= 1'b0;
else
outclk <= outclk_n;
end
//组合电路,设置在定时器最后2个脉冲拉高
always @(*)
begin
if((timecnt == 4'd6 || timecnt == 4'd7) && key_expansion_busy == 1'b1)
outclk_n = 1'b1;
else
outclk_n = 1'b0;
end
//时序电路,设置输出有效信号
always @(posedge clk_sys,negedge reset_sys_n)
begin
if(!reset_sys_n)
crypto_rnd_key_vld <= 1'b0;
else
crypto_rnd_key_vld <= crypto_rnd_key_vld_n;
end
//组合电路,设置在定时器最后2个脉冲拉高
always @(*)
begin
if(key_expansion_run == 1'b0 && outclk == 1'b1) //key_expansion_run信号为0
crypto_rnd_key_vld_n = 1'b1;
else
crypto_rnd_key_vld_n = 1'b0;
end
//时序电路,初始化轮密钥计数器
always @(negedge outclk,negedge reset_sys_n)
begin
if(!reset_sys_n)
i <= 1'b0;
else
i <= i_n;
end
//组合电路,轮密钥计数
always