FPGA 经典题

1.12小时制时钟

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    reg [7:0] dhh,dmm,dss;
    reg [2:0] enable;
    wire load;
    BCD60 B0(clk,reset,enable[0],,dss[7:0],ss[7:0]);
    BCD60 B1(clk,reset,enable[1],,dmm[7:0],mm[7:0]);
    BCD60 B2(clk,,enable[2],load,dhh[7:0],hh[7:0]);
    
    assign enable={mm=={4'd5,4'd9}&ss=={4'd5,4'd9},
                   ss=={4'd5,4'd9},
                   ena};
    assign load=reset|(hh=={4'd1,4'd2}&mm=={4'd5,4'd9}&ss=={4'd5,4'd9});
    assign dhh=reset?{4'd1,4'd2}:{4'b0,4'b1};
    always@(posedge clk)begin
        if (hh=={4'd1,4'd1}&mm=={4'd5,4'd9}&ss=={4'd5,4'd9}&ena)
            pm<=~pm;
    end
endmodule
            
module BCD60(
       input clk,
       input reset,
       input enable,
       input load,
       input [7:0] d,
       output [7:0] q );
    always@(posedge clk)begin
        if(reset)
            q<=8'b0;
        else if(load)
            q<=d;
        else if ((q[7:4]>=4'd5)&(q[3:0]>=4'd9)&(enable))
            q<=8'b0;
        else if((q[3:0]>=4'd9)&(enable))
            q<={q[7:4]+4'b1,4'b0};
        else if(enable)
            q[3:0]<=q[3:0]+4'b1;
    end
endmodule