119. Fsm1
尽量用写时序电路,避免竞争冒险
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output reg out);//
parameter A=0, B=1;
reg state, next_state;
always@(posedge clk or posedge areset)
begin
if(areset) next_state = 1;
else
begin
case (state)
A :
begin
if(in == 0) next_state = B;
else next_state = A;
end
default :
begin
if(in == 0) next_state = A;
else next_state = B;
end
endcase
end
state = next_state;
case(state)
A : out = 0;
default : out = 1;
endcase
end
endmodule
120. Fsm1s
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 0, B = 1;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
next_state = B;
end else begin
case (present_state)
A :
begin
if(in == 0) next_state = B;
else next_state = A;
end
B:
begin
if(in == 0) next_state = A;
else next_state = B;
end
endcase
end
// State flip-flops
present_state = next_state;
case (present_state)
A : out = 0;
B : out = 1;
endcase
end
endmodule
121. Fsm2
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output reg out); //
parameter OFF=0, ON=1;
reg state, next_state;
always@(posedge clk or posedge areset)
begin
if(areset) next_state = OFF;
else
begin
case (state)
OFF :
begin
if(j == 0) next_state = OFF;
else next_state = ON;
end
default :
begin
if(k == 0) next_state = ON;
else next_state = OFF;
end
endcase
end
state = next_state;
case (state)
OFF : out = 0;
default : out = 1;
endcase
end
endmodule
113. Fsm2s
module top_module(
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output reg out); //
parameter OFF=0, ON=1;
reg state, next_state;
always@(posedge clk)
begin
if(reset) next_state = OFF;
else
begin
case (state)
OFF :
begin
if(j == 0) next_state = OFF;
else next_state = ON;
end
default :
begin
if(k == 0) next_state = ON;
else next_state = OFF;
end
endcase
end
state = next_state;
case (state)
OFF : out = 0;
default : out = 1;
endcase
end
endmodule
114. Fsm3comb
module top_module(
input in,
input [1:0] state,
output reg [1:0] next_state,
output reg out); //
parameter A=0, B=1, C=2, D=3;
always@(*)
begin
case(state)
A :
begin
if(in == 0) next_state = A;
else next_state = B;
out = 0;
end
B :
begin
if(in == 0) next_state = C;
else next_state = B;
out = 0;
end
C :
begin
if(in == 0) next_state = A;
else next_state = D;
out = 0;
end
default :
begin
if(in == 0) next_state = C;
else next_state = B;
out = 1;
end
endcase
end
endmodule
115. Fsm3onehot
画状态转移图,四个状态的值决定了他们可以由state[A/B/C/D]来表示。
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = ((state[A]) && (in == 0)) || ((state[C]) && (in == 0));
assign next_state[B] = ((state[A]) && (in == 1)) || ((state[B]) && (in == 1)) || ((state[D]) && (in == 1));
assign next_state[C] = ((state[B]) && (in == 0)) || ((state[D]) && (in == 0));
assign next_state[D] = ((state[C]) && (in == 1));
// Output logic:
assign out = (state[D]);
endmodule
116.Fsm3
module top_module(
input clk,
input in,
input areset,
output reg out); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, next_state;
always@(posedge clk or posedge areset)
begin
if(areset) next_state = A;
else
begin
case (state)
A:
if(in) next_state = B;
else next_state = A;
B:
if(in) next_state = B;
else next_state = C;
C:
if(in) next_state = D;
else next_state = A;
default:
if(in) next_state = B;
else next_state = C;
endcase
end
state = next_state;
case (state)
D : out = 1;
default : out = 0;
endcase
end
endmodule
117. Fsm3s
module top_module(
input clk,
input in,
input reset,
output reg out); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, next_state;
always@(posedge clk)
begin
if(reset) next_state = A;
else
begin
case (state)
A:
if(in) next_state = B;
else next_state = A;
B:
if(in) next_state = B;
else next_state = C;
C:
if(in) next_state = D;
else next_state = A;
default:
if(in) next_state = B;
else next_state = C;
endcase
end
state = next_state;
case (state)
D : out = 1;
default : out = 0;
endcase
end
endmodule