参考
说明:
- 生成多项式最高次r次(r次和0次不能为0),对应LFSR触发器有r级,先画电路图,从最高位反馈
- LFSR初值为全0
- 待测序列n位,需要扩充至n+r位,按照LFSR移位n+r位,由于LFSR初值为0,因此开始的n次把待测序列移位进入LFSR
以下例子中,G(x) = x4 + x2 + 1(r = 4),M(x) = 8’b11011011,模拟过程+VCS仿真:
VCS:
schematic:
校验过程,是将M(x)与CRC余数拼接,再与G(x)模二除法,结果为0则校验成功。
csde
module crc(
input clk,
input rst_n,
input start,
input [7 : 0]data,
output [3 : 0] crc,
output vld
);
//================parameter
parameter IDLE = 2'b00;
parameter LFSR = 2'b01;
parameter END = 2'b10;
//================defination
reg [1 : 0] state, state_n;
reg [3 : 0] lfsr;
reg [3 : 0] cnt;
wire add_cnt;
wire end_cnt;
reg [7 : 0] data_in;
//================output
always@(posedge clk or negedge rst_n)begin
if(!rst_n) state <= IDLE;
else state <= state_n;
end
always@(*)begin
case(state)
IDLE : if(start) state_n = LFSR; else state_n = IDLE;
LFSR : if(end_cnt) state_n = END; else state_n = LFSR;
END : state_n = IDLE;
default : state_n = IDLE;
endcase
end
assign add_cnt = (state == LFSR);
assign end_cnt = add_cnt && (cnt == 11);
always@(posedge clk or negedge rst_n)begin
if(!rst_n) cnt <= 'd0;
else if(end_cnt) cnt <= 'd0;
else if(add_cnt) cnt <= cnt + 1'b1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n) lfsr <= 'd0;
else if(state == END) lfsr <= 'd0;
else if(state == LFSR)begin
lfsr[0] <= lfsr[3] ^ data_in[7];
lfsr[1] <= lfsr[0];
lfsr[2] <= lfsr[3] ^ lfsr[1];
lfsr[3] <= lfsr[2];
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n) data_in <= 'd0;
else if(start) data_in <= data;
else if(state == LFSR) data_in <= data_in << 1;
end
assign crc = lfsr;
assign vld = (state == END);
endmodule