hdlbits_Fsm_onehot

1. 1有error,但是我认为逻辑没错

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
	
    parameter S0 = 10'h1,S1 =10'h2,S2=10'h4,S3=10'h8,S4=10'h10,S5=10'h20,S6=10'h40,S7=10'h80,S8=10'h100,S9=10'h200;
    
    always @(*)
        begin
            case(state)
                S0: next_state = in?S1:S0;
                S1: next_state = in?S2:S0;
                S2: next_state = in?S3:S0;
                S3: next_state = in?S4:S0;
                S4: next_state = in?S5:S0;
                S5: next_state = in?S6:S8;
                S6: next_state = in?S7:S9;
                S7: next_state = in?S7:S0;
                S8: next_state = in?S1:S0;
                S9: next_state = in?S1:S0;
                default: next_state = 0;
            endcase
        end
       /*         
    always @(*)
        begin
            state = next_state;
        end
    */
    assign out1 = (state ==S8) | (state ==S9);
    assign out2 = (state ==S7) | (state ==S9);
endmodule

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
	
    parameter S0 = 0,S1 =1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8,S9=9;
    
    assign next_state[0] = (state[0]==1& (~in)) | 
        (state[1]==1& (~in)) | 
        (state[2]==1& (~in)) | 
        (state[3]==1& (~in))|
        (state[4]==1& (~in)) |
        (state[7]==1& (~in)) |(state[8]==1& (~in)) |(state[9]==1& (~in));
    assign next_state[1] = (state[0]==1& (in)) | (state[8]==1& (in))|(state[9]==1& (in));
    assign next_state[2] = (state[1]==1& (in));
    assign next_state[3] = (state[2]==1& (in));
    assign next_state[4] = (state[3]==1& (in));
    assign next_state[5] = (state[4]==1& (in));
    assign next_state[6] = (state[5]==1& (in));
    assign next_state[7] = (state[6]==1& (in)) | (state[7]==1& (in));
    assign next_state[8] = (state[5]==1& (~in));
    assign next_state[9] = (state[6]==1& (~in));
    
    
    assign out1 = (state[8] ==1) | (state[9] ==1);
    assign out2 = (state[7] ==1) | (state[9] ==1);
endmodule