HDLBits：Serial Receiver系列问题

1.Serial receiver

解析：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
parameter IDLE=0,START=1,DATA=2,STOP=3,ERROR=4;
    reg[2:0] state,next;
    reg[3:0] cnt;
    
  //计数器，用于判断DATA输入的位数
    always@(posedge clk )
        begin
            if(reset)
                cnt<=4'b0000;
            else if(next==DATA)
                cnt<=cnt+1'b1;
            else cnt<=4'b0000;
        end
   
   //驱动
    always@(*)
        begin
            case(state)
                IDLE:next=(in)?IDLE:START;
                START:next=DATA;
                DATA:next=(cnt==4'b1000)?((in)?STOP:ERROR):DATA;
                STOP:next=(in)?IDLE:START;
                ERROR:next=(in)?IDLE:ERROR;
            endcase
        end
    //状态
    always@(posedge clk )
          begin
              if(reset)
                  state<=IDLE;
              else state<=next;
          end

    //输出      
    assign done = (state==STOP);
endmodule

2.

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

parameter IDLE=0,START=1,DATA=2,STOP=3,ERROR=4;
    reg[2:0] state,next;
    reg[3:0] cnt;
    reg[7:0] out;
  // Use FSM from Fsm_serial  
  //计数器，用于判断DATA输入的位数
    always@(posedge clk )
        begin
            if(reset)
                cnt<=4'b0000;
            else if(next==DATA)
                cnt<=cnt+1'b1;
            else cnt<=4'b0000;
        end
 
   
   //驱动
    always@(*)
        begin
            case(state)
                IDLE:next=(in)?IDLE:START;
                START:next=DATA;
                DATA:next=(cnt==4'b1000)?((in)?STOP:ERROR):DATA;
                STOP:next=(in)?IDLE:START;
                ERROR:next=(in)?IDLE:ERROR;
            endcase
        end
    //状态
    always@(posedge clk )
          begin
              if(reset)
                  state<=IDLE;
              else state<=next;
          end
           
    assign done = (state==STOP);
    assign out_byte =(done)?out:8'b0;

  // New: Datapath to latch input bits.
  //定义一个移位寄存器来存输入数据
    always@(posedge clk )
        begin
            if(reset)
                out<=8'bX;
            else if(next==DATA)
                out<={in,out[7:1]};

        end
endmodule