HDLBits：状态机（FSM）之“Serial receiver”系列

目录

Serial receiver

Serial receiver and datapath

Serial receiver with parity checking

---

Serial receiver

题链接：Fsm serial - HDLBits (01xz.net)

• DATA 状态合并了图中的 “stop”，共在此状态 9 clk

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    // state define
    parameter WAIT=2'd0, DATA=2'd1, DONE=2'd2, ERROR=2'd3;
    reg [1:0] state, next_state;
    int count; // count DATA bytes
    
    // state transition logic
    always @(*) begin
        case(state)
            WAIT: next_state = in ? WAIT : DATA;
            DATA: begin
                if(count < 8) next_state = DATA;
                else if(in) next_state = DONE;
                else next_state = ERROR;
            end
            DONE: next_state = in ? WAIT : DATA;
            ERROR: next_state = in ? WAIT : ERROR;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset) begin
            state <= WAIT;
            count <= 0;
        end
        else begin
            state <= next_state;
            if(state==DATA && count<8)
                count <= count + 1;
            else count <= 0;
        end
    end
    
    assign done = (state == DONE);

endmodule

---

Serial receiver and datapath

题链接：Fsm serialdata - HDLBits (01xz.net)

• 利用上一题 count 即可完成

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); 
    // Use FSM from Fsm_serial
    // 此处省略上一题代码...

    // New: Datapath to latch input bits.
    always @(posedge clk) begin
        if(next_state == DATA && count < 8) 
            out_byte[count] = in;
        // else keep
    end

endmodule

---

Serial receiver with parity checking

题链接：Fsm serialdp - HDLBits (01xz.net)

• 8 bytes 数据后多一位奇偶校验，合并入 DATA 状态（DATA 态合计 10 clk），注意“state transition logic”的 DATA 部分跳转
• “odd checking”部分用的时序逻辑，没用题设的 parity module
• 较之上题代码，修改部分注释“modify”

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); 
    // Use FSM from Fsm_serial
    parameter WAIT=2'd0, DATA=2'd1, DONE=2'd2, ERROR=2'd3;
    reg [1:0] state, next_state;
    int count; // count DATA bytes
    reg odd;
    
    // state transition logic
    always @(*) begin
        case(state)
            WAIT: next_state = in ? WAIT : DATA;
            // modify DATA case item
            DATA: 
            begin
                if(count == 9)  next_state = in ? (odd ? DONE : WAIT) : ERROR;
                else next_state = DATA;
            end
            DONE: next_state = in ? WAIT : DATA;
            ERROR: next_state = in ? WAIT : ERROR;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset) begin
            state <= WAIT;
            count <= 0;
        end
        else begin
            state <= next_state;
            if(state==DATA && count<9) // modify 8 -> 9
                count <= count + 1;
            else count <= 0;
        end
    end
    
    assign done = (state == DONE);

    // Datapath to latch input bits.
    always @(posedge clk) begin
        if(next_state == DATA && count < 8) 
            out_byte[count] = in;
        // else keep
    end
    
    // New: odd part
    always @(posedge clk) begin
        if(reset) odd <= 1'b0;
        /* modify 
         bit流顺序框架“data 1~8 bytes --- parity check --- ‘in’ check --- DONE or WAIT or ERROR”
         “count<9”时进行8bytes数据和parity进行校验，“count==9”时进入第10字节“stop”位，此位不计入奇偶校验，故而保持odd不变用于“state transition logic”跳转判断*/
        else if(next_state == DATA) odd <= (count<9) ? (in ? ~odd : odd) : odd; 
        else odd <= 1'b0;      
    end 


endmodule