verilog练习：hdlbits网站上的做题笔记（5）

前言

• 之前的文章《如何学习verilog，如何快速入门？》中提到了verilog学习，推荐了一个可以练习的网站：hdlbits网站，那自己也玩玩这个网站。

• 这篇文章，是接着《verilog练习：hdlbits网站上的做题笔记（4）》写的！

3.2 Sequential Logic

3.2.1 Latches and Flip-Flops

3.2.1.1 D flip-flop（Dff）

A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.
D flip-flops are created by the logic synthesizer when a clocked always block is used . A D flip-flop is the simplest form of “blob of combinational logic followed by a flip-flop” where the combinational logic portion is just a wire.
Create a single D flip-flop.

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always@(posedge clk)begin
    	q <= d;
    end
endmodule

3.2.1.2 D flip-flops（dff8）

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
	always@(posedge clk)begin
    	q <= d;
    end
endmodule

3.2.1.3 DFF with reset（Dff8r）

创建具有高电平有效同步复位的8 D触发器。所有DFF应由clk的上升沿触发。

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
	always@(posedge clk)begin//同步复位的D触发器
        if(reset)
            q <= 'd0;
        else
    		q <= d;
    end
endmodule

3.2.1.4 DFF with reset value（Dff8p）

Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    
    always@(negedge clk)begin//同步复位的D触发器,复位值为34
        if(reset)
            q <= 'h34;
        else
    		q <= d;
    end
endmodule

3.2.1.5 DFF with asynchronous reset（Dff8ar）

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset )begin//异步复位的触发器（复位与寄存不能一起操作）
        if(areset)
            q <= 'd0;
        else
    		q <= d;
    end

endmodule

3.2.1.6 DFF with byte enable（Dff16e）

Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].

resetn is a synchronous, active-low reset.
All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk)begin
        if(!resetn)
            q<='d0;
        else
            case(byteena)
                2'b11:q<=d;
                2'd10:q[15:8]<=d[15:8];
                2'b01:q[7:0]<=d[7:0];
                default:q<=q;
            endcase
    end
    

endmodule

3.2.1.7 D Latch（Exams/m2014 q4a）

锁存器

//书上都说，不补全if...else...，case等可能会产生锁存器，
//但是我想问问，锁存器与寄存器的区别是什么？
//为什么下面这个,补全了else，还是生成了锁存器？
module top_module (
    input d, 
    input ena,
    output q);
    always@(*)
        if(ena)
            q = d;
        else
            q = q;
endmodule

3.2.1.8 DFF（Exams/m2014 q4b）

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always@(posedge clk or posedge ar)
        if(ar)
        q <= 'd0;
    else
        q<=d;
endmodule

3.2.1.9 DFF（Exams/m2014 q4c）

同步复位

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always@(posedge clk)
    if(r)
        q <= 'd0;
    else
        q <= d;
endmodule

3.2.1.10 DFF+gate（Exams/m2014 q4d）

实现以下这个电路

module top_module (
    input clk,
    input in, 
    output out);
    
    always@(posedge clk)
        out <= in^out;

endmodule

3.2.1.11 Mux and DFF(mt2015_muxdff)

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    always@(posedge clk)
        if(L)
            Q <= r_in;
    	else
            Q <= q_in;

endmodule

3.2.1.12 Mux and DFF（Exams/2014 q4a）

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    always@(posedge clk)begin
        if(L)
            Q <= R;
        else if(E)
            Q <= w;
        else 
            Q<= Q;
    end
endmodule

3.2.1.13 DFFs and gates（Exams/2014 q4a）

module top_module (
    input clk,
    input x,
    output z
); 
    reg [2:0] q;
    always@(posedge clk)
        q <= {
   
   x|~q[2],x& ~q[1],x^q[0]};
        
    assign z = ~(|q);

endmodule

3.2.1.14 Create circuit from truth table（Exams/ece241 2013 q7）

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    always@(posedge clk)
        case({
   
   j,k})
            2'b00:Q<= Q;
            2'b01:Q<= 0;
            2'b10:Q<= 1;
            2'b11:Q<=~Q;
            default:;
        endcase

endmodule

3.2.1.15 Detect an edge（Edgedetect）

//第一种方法，最常见的
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] reg_in;
    always@(posedge clk)
        reg_in <= in;
    
    always@(posedge clk)
        pedge <= ~reg_in & in;

endmodule

//另一种思路
module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] reg_in;
    always@(posedge clk)
        reg_in <= in;
    
    integer i;
    always@(posedge clk)begin
        for(i = 0; i <= 7; i = i + 1)begin
            if(in[i] & ~reg_in[i])begin
                pedge[i] <= 1'b1;
            end
            else begin
                pedge[i] <= 1'b0;
            end
        end
    end

endmodule

3.2.1.16 Detect both edges（Edgedetect2）

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
	reg [7:0] reg_in;
    always@(posedge clk)
        reg_in <= in;
    
    always@(posedge clk)
        anyedge <= reg_in ^ in;
endmodule

3.2.1.17 Edge capture register（Edgecapture）

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).
捕获到下降沿一直保持为1，直到复位信号为1才变位0
Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    wire [31:0] nedge;
    reg [31:0] reg_in;
   
    always@(posedge clk)
        reg_in <= in;
    
    assign 	nedge = reg_in & ~in;//下降沿检测
    always@(posedge clk)begin
        if(reset)
                out<= 0;
        else if(nedge!=0)
                out<=nedge|out;
        else
                out<=out;  
    end
     
endmodule

3.2.1.18 Dual-edge triggered flip-flop（Dualedge）

您熟悉在时钟的上升沿或时钟的下降沿触发的触发器。双沿触发触发器在时钟的两个边沿触发。但是，FPGA没有双沿触发触发器，因此始终不接受@（posedge clk或negedge clk）作为合法敏感性列表。