偶数分频器6分频

module divider_six(
	input wire sys_clk,
	input wire sys_rst_n,
	output reg clk_out
    );
	
	reg [1:0]cnt;
	always@(posedge sys_clk or negedge sys_rst_n)
		begin
			if(sys_rst_n==0)
				cnt<=0;
			else if(cnt==2'b10)
				cnt<=0;
			else
				cnt<=cnt+2'b1;
		end
		
	always@(posedge sys_clk or negedge sys_rst_n)
		begin
			if(sys_rst_n==0)
				clk_out<=0;
			else if(cnt==2'b10)
				clk_out<=~clk_out;
			else
				clk_out<=clk_out;
		end
	
	
endmodule

 测试代码

`timescale 1ns / 1ns

module tb_divider_six();

reg sys_clk;
reg sys_rst_n;
wire clk_out;

initial
	begin
		sys_clk=1'b1;
		sys_rst_n<=1'b0;;
		#20
		sys_rst_n<=1'b1;
	end
always #10 sys_clk=~sys_clk;

divider_six divider_six_inst(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.clk_out(clk_out)
    );

endmodule

也可以用脉冲的方法

`timescale 1ns / 1ns
module divider_six(
	input wire sys_clk,
	input wire sys_rst_n,
	output reg clk_flag
    );
	
	reg [2:0]cnt;
always@(posedge sys_clk or negedge sys_rst_n)
		begin
			if(sys_rst_n==3'd0)
				cnt<=3'd0;
			else if(cnt==3'd5)
				cnt<=3'd0;
			else
				cnt<=cnt+3'd1;
		end
		always@(posedge sys_clk or negedge sys_rst_n)
		begin
			if(sys_rst_n==3'd0)
				clk_flag<=3'd0;
			else if(cnt==3'd4)
				clk_flag<=3'd1;
			else
				clk_flag<=3'd0;
		end
	
endmodule

测试代码

`timescale 1ns / 1ns

module tb_divider_six();

reg sys_clk;
reg sys_rst_n;
wire clk_flag;

initial
	begin
		sys_clk=1'b1;
		sys_rst_n<=1'b0;;
		#20
		sys_rst_n<=1'b1;
	end
always #10 sys_clk=~sys_clk;

divider_six divider_six_inst(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.clk_flag(clk_flag)
    );

endmodule

vivado仿真波形图