FPGA TESTBENCH读取文件数据
`timescale 1ns / 1ps
// Company:
// Engineer:
//
// Create Date: 13:44:03 12/09/2020
// Design Name: Fir_Filt_top
// Module Name: E:/FPGA_CODE/source/Fir_Filt_top_TB.v
// Project Name: FIR_FILTER_TOP
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Fir_Filt_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module Fir_Filt_top_TB;
// Inputs
reg I_clk;
reg I_rst;
reg I_raw_data_vld;
reg [15:0] I_raw_data;
// Outputs
wire [31:0] O_float_dout;
// Instantiate the Unit Under Test (UUT)
Fir_Filt_top uut (
.I_clk(I_clk),
.I_rst(I_rst),
.I_raw_data_vld(I_raw_data_vld),
.I_raw_data(I_raw_data),
.O_float_dout(O_float_dout)
);
parameter MemLen = 512; // 512 * 1
reg [15 : 00] mem_raw_data [0 : MemLen];
reg Start_flag = 0;
integer index = 0;
integer j = 0;
initial begin
// Initialize Inputs
I_clk = 0;
I_rst = 1;
I_raw_data_vld = 0;
I_raw_data = 0;
Start_flag = 0;
// Wait 100 ns for global reset to finish
#1000; I_rst = 0;
#1000; Start_flag = 1;
// Add stimulus here
end
initial begin
$readmemh ( "E:/Aligei_WaveMeter/FPGA_CODE/Algorithm/ST/Algo_Design/FIR_filter_demo/FIR_FILTER_TOP/source/raw_data.dat", mem_raw_data, 0, MemLen);
end
initial begin
#2000;
while(1)begin
j = j + 1;
if((j>=10) & (j <= 521))begin
index = index + 1;
I_raw_data_vld = 1;
I_raw_data = mem_raw_data[index-1];
end
else if(j == 522)begin
I_raw_data_vld = 0;
index = 0;
end
else if(j == 530)begin
j = 0;
end
#10;
end
end
always #5 I_clk = ~I_clk;
// reg [31:00] index = 0;
// reg [31:00] j = 0;
endmodule