module halfadd( input wire in_1,
input wire in_2,
output wire count,//进位
output wire sum
);
///方法一,拼接形式
assign {count,sum}=in_1+in_2;
//方法二
//assign count = in_1 & in_2;
//assign sum = in_1 ^ in_2;
endmodule
module vtf_halfadd;
// Inputs
reg in_1;
reg in_2;
// Outputs
wire count;
wire sum;
// Instantiate the Unit Under Test (UUT)
halfadd uut (
.in_1(in_1),
.in_2(in_2),
.count(count),
.sum(sum)
);
initial begin
// Initialize Inputs
in_1 = 0;
in_2 = 0;
// Wait 100 ns for global reset to finish
#100;
in_1 = 0;
in_2 = 0;
#100;
in_1 = 1;
in_2 = 1;
#100;
in_1 = 0;
in_2 = 1;
#100;
in_1 = 1;
in_2 = 0;
#100
$stop;
// Add stimulus here
end
endmodule