verilog刷题笔记004

最新推荐文章于 2024-11-02 06:00:00 发布

xiaobaibaizzf

最新推荐文章于 2024-11-02 06:00:00 发布

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本文链接：https://blog.csdn.net/cxiaobaizzf/article/details/123957731

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Verilog 状态机游戏逻辑 Lemmings 行为模拟

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Lemmings4的一种解法

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    reg [7:0] state;
    reg [7:0] next_state;
    parameter LEFT = 0, DIG_L = 1, FALL_L = 2,
    		 RIGHT = 3, DIG_R = 4, FALL_R = 5,
             SPLAT = 6;
    
    always@(*)begin
        case(state[2:0])
            LEFT:begin
                if(ground == 0) next_state = FALL_L;
                else begin
                    if(dig) next_state = DIG_L;
                    else begin
                        if(bump_left) next_state = RIGHT;
                        else next_state = LEFT;
                    end
                end
            end
            DIG_L:begin
                if(ground == 0) next_state = FALL_L;
                else next_state = DIG_L;
            end
            FALL_L:begin
                if(ground == 1&&state[7:3]<5'd20) next_state = LEFT;
                else if(ground == 1&&state[7:3]>=5'd20) next_state = SPLAT; 
                else begin
                    if(state[7:3]<5'd20) next_state = state + 8;
                    else begin
                        next_state = state;
                    end
                end
            end
            RIGHT:begin
                if(ground == 0) next_state = FALL_R;
                else begin
                    if(dig) next_state = DIG_R;
                    else begin
                        if(bump_right) next_state = LEFT;
                        else next_state = RIGHT;
                    end
                end
            end
            DIG_R:begin
                if(ground == 0) next_state = FALL_R;
                else next_state = DIG_R;
            end
            FALL_R:begin
                if(ground == 1&&state[7:3]<5'd20) next_state = RIGHT;
                else if(ground == 1&&state[7:3]>=5'd20) next_state = SPLAT; 
                else begin
                    if(state[7:3]<5'd20) next_state = state + 8;
                    else begin
                        next_state = state;
                    end
                end
            end 
            SPLAT: next_state = SPLAT;
        endcase
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset) begin
            state <= 0;
        end
        else state <= next_state;
    end
    
    assign walk_left = ~(state == SPLAT)&(state[2:0] == LEFT);
    assign walk_right= ~(state == SPLAT)&(state[2:0] == RIGHT);
    assign aaah =      ~(state == SPLAT)&((state[2:0] == FALL_L)|(state[2:0] == FALL_R));
    assign digging =   ~(state == SPLAT)&((state[2:0] == DIG_L)|(state[2:0] == DIG_R));
    
    

endmodule