verilog刷题笔记3-verilog language

三、module

1.实例化

1.by position

mod_a instance1 ( wa, wb, wc );

2.by name

mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );

module top_module ( input a, input b, output out );
    //mod_a ins (a,b,out);
    mod_a ins (.in1(a), .in2(b),.out(out));

endmodule

2.多模块实例化 

给定模块: module my_dff ( input clk, input d, output q );