赛灵思的block memory generator用户手册pg058翻译和学习（管脚描述Native Block Memory）

读赛灵思IP手册，block memory generator Product Guide，即内存memory系列（如RAM ROM等）的手册。本期介绍Chapter2的Product Specification 管脚描述Native Block Memory。

P30

Port Descriptions

Native Block Memory Generator Signals

Table 2-5 provides a description of the Block Memory Generator core signals. You can select the widths of the data ports (dina, douta, dinb, and doutb) in Vivado IDE. The address port (addra and addrb) widths are determined by the memory depth with respect to each port. The Write enable ports (wea and web) are buses of width 1 when byte-writes are disabled. When byte-writes are enabled, wea and web widths depend on the byte size and Write data widths selected in Vivado IDE.

端口说明

Native Block Memory Generator信号

表2-5提供了BMG IP核信号的描述。您可以在Vivado IDE中选择数据端口的宽度（dina、douta、dinb和doutb）。地址端口（addra和addrb）宽度由每个端口的内存深度决定。当字节写入被禁用时，写入启用端口（wea和web）是宽度为1的总线。启用字节写入时，wea和web宽度取决于Vivado IDE中选择的字节大小和写入数据宽度。

Table 2-5: Core Signal Pinout

Name	Direction	Description
clka	Input	Port A Clock: Port A operations are synchronous to this  clock. For synchronous operation, this must be driven by the same signal as CLKB.端口A时钟：端口A操作与此时钟同步。对于同步操作，必须由与CLKB相同的信号驱动。
addra	Input	Port A Address: Addresses the memory space for port A Read  and Write operations. Available in all configurations.为端口A读取和写入操作寻址内存空间。可用于所有配置。
dina	Input	Port A Data Input: Data input to be written into the memory  through port A. Available in all RAM configurations.通过端口A将数据输入写入存储器。在所有RAM配置中都可用。
douta	Output	Port A Data Output: Data output from Read operations through port  A. Available in all configurations except Simple Dual-port RAM.从读取操作通过端口A输出的数据。除简单双端口RAM外，所有配置均可用。
ena	Input	Port A Clock Enable: Enables Read, Write, and reset operations through  port A. Optional in all configurations.通过端口A启用读取、写入和重置操作。在所有配置中都是可选的。
wea	Input	Port A Write Enable: Enables Write operations through port A. Available  in all RAM configurations.通过端口A启用写入操作。在所有RAM配置中都可用。
rsta	Input	Port A Set/Reset: Resets the Port A memory output latch or  output register. Optional in all configurations.复位端口A内存输出锁存器或输出寄存器。在所有配置中都是可选的。
regcea	Input	Port A Register Enable: Enables the last output register of port A. Optional  in all configurations with port A output registers.启用端口A的最后一个输出寄存器。在端口A输出寄存器的所有配置中都是可选的。
clkb	Input	Port B Clock: Port B operations are synchronous to this  clock. Available in dual-port configurations. For synchronous operation, this
		must  be driven by the same signal as CLKA.
		端口B操作与该时钟同步。提供双端口配置。对于同步操作
		必须由与CLKA相同的信号驱动。
addrb	Input	Port B address: Addresses the memory space for port B Read  and Write operations. Available in dual-port configurations为端口B读取和写入操作寻址内存空间。提供双端口配置
.
dinb	Input	Port B Data Input: Data input to be written into the memory through  port B. Available in True Dual-port RAM configurations.通过端口B将数据输入写入内存。在真双端口RAM配置中可用。
doutb	Output	Port B Data Output: Data output from Read operations through Port  B. Available in dual-port configurations.通过端口B从读取操作输出的数据。在双端口配置中可用。
enb	Input	Port B Clock Enable: Enables Read, Write, and reset operations through  Port B. Optional in dual-port configurations.通过端口B启用读取、写入和重置操作。双端口配置中可选。
web	Input	Port B Write Enable: Enables Write operations through Port B. Available  in Dual-port RAM configurations.
		通过端口B启用写入操作。在双端口RAM配置中可用。
rstb	Input	Port B Set/Reset: Resets the Port B memory output latch or output  register. Optional in all configurations.重置端口B内存输出锁存器或输出寄存器。在所有配置中都是可选的。
regceb	Input	Port B Register Enable: Enables the last output register of port B. Optional  in dual-port configurations with port B output registers.启用端口B的最后一个输出寄存器。在具有端口B输出寄存器的双端口配置中可选。
sbiterr	Output	Single-Bit Error: Flags the presence of a single-bit error in  memory which has been auto-corrected on the output bus.标志在输出总线上已自动纠正的存储器中存在一位错误。
dbiterr	Input	Double-Bit Error: Flags the presence of a double-bit error in  memory. Double-bit errors cannot be auto-corrected by the built-in ECC decode  module.标记内存中存在双位错误。内置ECC解码模块无法自动纠正双位错误。
injectsbiterr	Input	Inject Single-Bit Error: Available only for Zynq-7000 and 7 series ECC  configurations
injectdbiterr	Input	Inject Double-Bit Error: Available only for Zynq-7000 and 7 series ECC  configurations.仅适用于Zynq-7000和7系列ECC配置
rdaddrecc	Output	Read Address for ECC Error output: Available only for  Zynq-7000 and 7 series ECC configurations.ECC错误输出的读取地址：仅适用于Zynq-7000和7系列ECC配置。
eccpipece	Input	ECC Pipe Line Register Clock Enable: Available only for  UltraScale architecture-based devices.ECC流水线寄存器时钟启用：仅适用于基于UltraScale体系结构的设备。
sleep	Input	Dynamic Power Saving: If sleep pin is High , the Block Memory Generator  core is in power saving mode. Available only for UltraScale architecture-based  devices.动态省电：如果休眠引脚为高，则块内存生成器内核处于省电模式。仅适用于基于UltraScale体系结构的设备。