名称:VGA显示器的弹球游戏DE1-SoC开发板乒乓球小球游戏VHDL
软件:Quartus II
语言:VHDL
代码功能:
弹球游戏
设计一个弹球游戏,并在VGA显示器上显示
1、可以控制游戏开始,开始时数码管显示0分
2、使用按键控制球拍的运动,当控制球拍接住球时,分数加1
3、弹球触碰屏幕边缘或者球拍时可以反弹
4、可以控制小球的移动速度和球拍的大小
4、当未成功接球时,游戏结束
本代码已在DE1-SoC开发板验证,其他开发板可以修改管脚适配,开发板如下:
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
代码下载:
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; --顶层模块 ENTITY vga_controller_top IS PORT ( clk_50M : IN STD_LOGIC;--时钟 rst : IN STD_LOGIC;--复位 speed_sw : IN STD_LOGIC_VECTOR(1 DOWNTO 0);--速度控制按键 size_sw : IN STD_LOGIC_VECTOR(1 DOWNTO 0);--大小控制按键 btn_up : IN STD_LOGIC;--上下按键 btn_down : IN STD_LOGIC;--上下按键 hsync : OUT STD_LOGIC;--行场同步信号 vsync : OUT STD_LOGIC;--行场同步信号 VGA_CLK : OUT STD_LOGIC;--vga时钟 VGA_BLANK_N : OUT STD_LOGIC; HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);--数码管 rgb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)--VGA三色数据 ); END vga_controller_top; ARCHITECTURE behave OF vga_controller_top IS --复位按键同步模块 COMPONENT aiso_rst IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; reset_s : OUT STD_LOGIC ); END COMPONENT; --VGA同步模块 COMPONENT vga_sync IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; VGA_CLK : OUT STD_LOGIC; VGA_BLANK_N : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); pixel_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); video_on : OUT STD_LOGIC ); END COMPONENT; --按键同步模块 COMPONENT debounce IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; sw : IN STD_LOGIC; db : OUT STD_LOGIC ); END COMPONENT; --产生墙、球和球拍 COMPONENT graphic_generator IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; speed_sw : IN STD_LOGIC_VECTOR(1 DOWNTO 0); size_sw : IN STD_LOGIC_VECTOR(1 DOWNTO 0); btn : IN STD_LOGIC_VECTOR(1 DOWNTO 0); pixel_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0); pixel_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0); video_on : IN STD_LOGIC; score : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); rgb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; --数码管模块 COMPONENT display is PORT( score:IN STD_LOGIC_VECTOR(3 DOWNTO 0); HEX:out STD_LOGIC_VECTOR(6 DOWNTO 0) ); end COMPONENT; SIGNAL clk : STD_LOGIC:='0'; SIGNAL video_on : STD_LOGIC; SIGNAL rst_s : STD_LOGIC; SIGNAL pixel_x : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL pixel_y : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL db_btn_up : STD_LOGIC; SIGNAL db_btn_down : STD_LOGIC; SIGNAL btn_up_dowm : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL score : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Declare intermediate signals for referenced outputs SIGNAL hsync_buf : STD_LOGIC; SIGNAL vsync_buf : STD_LOGIC; SIGNAL rgb_buf : STD_LOGIC_VECTOR(11 DOWNTO 0); BEGIN -- Drive referenced outputs hsync <= hsync_buf; vsync <= vsync_buf; rgb <= rgb_buf; clk <= clk_50M; --复位按键同步模块 u0 : aiso_rst PORT MAP ( clk => clk, reset => rst, reset_s => rst_s ); --VGA同步模块 u1 : vga_sync PORT MAP ( clk => clk, rst => rst_s, VGA_CLK => VGA_CLK, VGA_BLANK_N => VGA_BLANK_N, hsync => hsync_buf, vsync => vsync_buf, pixel_x => pixel_x, pixel_y => pixel_y, video_on => video_on ); --按键同步模块 u2 : debounce PORT MAP ( clk => clk, reset => rst_s, sw => btn_up, db => db_btn_up ); --按键同步模块 u3 : debounce PORT MAP ( clk => clk, reset => rst_s, sw => btn_down, db => db_btn_down ); btn_up_dowm <= (db_btn_down & db_btn_up); --产生墙、球和球拍 u4 : graphic_generator PORT MAP ( clk => clk, rst => rst_s, btn => btn_up_dowm, pixel_x => pixel_x, pixel_y => pixel_y, speed_sw => speed_sw, size_sw => size_sw, video_on => video_on, score => score,--游戏分数 rgb => rgb_buf ); u5: display PORT MAP( score => score,--游戏分数 HEX => HEX ); END behave;
设计文档:
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
5. Testbench
6. 仿真图
整体仿真图
复位按键同步模块
VGA同步模块
按键同步模块
产生墙、球和球拍模块
数码管模块