名称:2位十进制计数器数码管显示设计VHDL代码modelsim仿真(文末获取)
软件:modelsim
语言:VHDL
代码功能:
2位十进制计数器数码管显示
1、计数0~99,计数到99回0
2、使用数码管显示
计数器
1. 程序文件
2. Testbench
3. 程序编译
4. 仿真图
复位清零
计数到99回到0 重新开始
数码管输出对应编码
数字锁
状态名 | 状态功能 | 输入(按键) | 输出(led) | |
idle | 空闲状态,等待输入按键值 | 输入密码按键后到s1状态 | 0 | |
S1 | 已输入1个密码值 | 输入密码按键后到s2状态 | 0 | |
S2 | 已输入2个密码值 | 输入密码按键后到s3状态 | 0 | |
S3 | 已输入3个密码值 | 输入密码按键后到s4状态 | 0 | |
S4 | 已输入4个密码值 | 无,自动跳转到s5状态 | 0 | |
S5 | 密码比对 | 无,若密码正确跳转到s6;若密码错误跳转到s5 | 0 | |
S6 | 密码正确 | 若有复位信号则回到idle,否则一直保持s6状态 | 1 | |
S7 | 密码错误 | 若有复位信号则回到idle,否则一直保持s7状态 | 0 |
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY counter IS PORT ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; digit1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); digit2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END counter; ARCHITECTURE behave OF counter IS SIGNAL cnt_10 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";--计数器十位 SIGNAL cnt_1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";--计数器个位 SIGNAL digit1_Hex : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; SIGNAL digit2_Hex : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; BEGIN PROCESS (clk, reset) BEGIN IF (reset = '1') THEN cnt_10 <= "0000"; cnt_1 <= "0000"; ELSIF (clk'EVENT AND clk = '1') THEN IF (cnt_10 = "1001" AND cnt_1 = "1001") THEN--计数到99时回0 cnt_10 <= "0000"; cnt_1 <= "0000"; ELSIF (cnt_1 = "1001") THEN--个位记到9以后十位进1 cnt_10 <= cnt_10 + "0001"; cnt_1 <= "0000"; ELSE cnt_10 <= cnt_10; cnt_1 <= cnt_1 + "0001";--计个位 END IF; END IF; END PROCESS; --7段数码管显示,低电平点亮, --第7位为小数点,第6位为g,第5位为f,第4位为e, --第3位为d,第2位为c,第1位为b,第0位为a, --数码管1 PROCESS (cnt_1) BEGIN CASE cnt_1 IS WHEN "0000" => digit1_Hex <= "11000000"; WHEN "0001" => digit1_Hex <= "11111001"; WHEN "0010" => digit1_Hex <= "10100100"; WHEN "0011" => digit1_Hex <= "10110000"; WHEN "0100" => digit1_Hex <= "10011001"; WHEN "0101" => digit1_Hex <= "10010010"; WHEN "0110" => digit1_Hex <= "10000010"; WHEN "0111" => digit1_Hex <= "11111000"; WHEN "1000" => digit1_Hex <= "10000000"; WHEN "1001" => digit1_Hex <= "10011000"; WHEN OTHERS => digit1_Hex <= "11000000"; END CASE;
源代码
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