RTL-CODING NOTE1

Port Ordering  

Use Function

Use Loops and Arrays (1)

Use Loops and Arrays (2)

Do Not Use Hard-Coded Numeric Value

Avoid Clock Buffers

 

Avoid Using Internally Generated Clocks
 

Gated Clocks and Low-Power Designs

Guideline:If the design requires a gated clock, model it in RTL using synchronous load registers.

Avoid Internally Generated Reset

Single-Bit Synchronizers

Multiple-Bit Synchronizer

Register

Avoid Latch

Make a Latch Testable—If you must use a latch

Case vs. If-Then-Else

Register All Outputs

Separate Modules That Have Different Design Goals