关于DDR3 IP核使用导入ucf文件，default设置的xilinx 报错处理记录

最新推荐文章于 2024-01-19 22:29:29 发布

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最新推荐文章于 2024-01-19 22:29:29 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/followless/article/details/132426247

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一导入ucf文件，synthesis，implementation后，生成bitstream报错

1：现象

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 118 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: calib_done, and error.

2：解决

点击Open Implemented Design,在右下方看到I/O Ports