锁存器的生成，两段式注意每个状态都要写信号值

只有在自己等于自己的 assign 中（包括没写全的case），才会生成电平敏感的 锁存器

参考FPGA之锁存器 - 皮皮祥 - 博客园

两段式注意跳转的时候 ，输出信号每个状态都要写，否则没写的状态下，此信号默认为0

    always @(posedge SCLK) begin
        if(RST) begin
            current_state <=  /* #TCQ */  RESTART;
        end else begin
            current_state <=  /* #TCQ */  next_state;
        end
    end

    always @* begin
        // Setup the default values
        next_srdy         = 1'b0;
        next_daddr        = DADDR;
        next_dwe          = 1'b0;
        next_den          = 1'b0;
        next_rst_mmcm     = RST_MMCM;
        next_di           = DI;
        next_rom_addr     = rom_addr;
        next_state_count  = state_count;

        case (current_state)
            RESTART: begin
                next_daddr     = 7'h00;
                next_di        = 16'h0000;
                next_rom_addr  = 6'h00;
                next_rst_mmcm  = 1'b1;
                next_state     = WAIT_LOCK;
            end

            WAIT_LOCK: begin
                next_rst_mmcm   = 1'b0;
                next_state_count = STATE_COUNT_CONST ;
                next_rom_addr = SADDR ? STATE_COUNT_CONST : 8'h00;

                if(IntLocked) begin
                    next_state  = WAIT_SEN;
                    next_srdy   = 1'b1;
                end else begin
                    next_state  = WAIT_LOCK;
                end
            end

            WAIT_SEN: begin
                next_rom_addr = SADDR ? STATE_COUNT_CONST : 8'h00;
                if (SEN) begin
                    next_state = ADDRESS;
                end else begin
                    next_state = WAIT_SEN;
                end
            end

            ADDRESS: begin
                next_rst_mmcm  = 1'b1;
                next_den       = 1'b1;
                next_daddr     = rom_do[38:32];

                next_state     = WAIT_A_DRDY;
            end

            WAIT_A_DRDY: begin
                if (DRDY) begin
                    next_state = BITMASK;
                end else begin
                    next_state = WAIT_A_DRDY;
                end
            end

            BITMASK: begin
                next_di     = rom_do[31:16] & DO;
                next_state  = BITSET;
            end

            BITSET: begin
                next_di           = rom_do[15:0] | DI;
                next_rom_addr     = rom_addr + 1'b1;
                next_state        = WRITE;
            end

            WRITE: begin
                next_dwe          = 1'b1;
                next_den          = 1'b1;

                next_state_count  = state_count - 1'b1;
                next_state        = WAIT_DRDY;
            end

            WAIT_DRDY: begin
                if(DRDY) begin
                    if(state_count > 0) begin
                        next_state  = ADDRESS;
                    end else begin
                        next_state  = WAIT_LOCK;
                    end
                end else begin
                    next_state     = WAIT_DRDY;
                end
            end

            default: begin
                next_state = RESTART;
            end
        endcase
    end
endmodule

上面的代码，next_srdy 只在 WAIT_LOCK 状态中赋值过，所以只有在此状态下 next_srdy = 1,其他状态下 next_srdy = 0,并且因为是 always @*， 所以next_srdy 只是一个 lut 输出，不是寄存器，也不是锁存器（不是0就是1）