1.普通4bit计数器,n位计数,2^n个状态:
module top_module ();
reg clk=0;
always #5 clk = ~clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram
`probe(clk); // Probe signal "clk"
// A testbench
reg reset;
initial begin
reset=0;
#10 reset=1;
$display ("Hello world! The current time is (%0d ps)", $time);
#50 $finish; // Quit the simulation
end
count inst1 (.clk(clk),.reset(reset)); // Sub-modules work too.
endmodule
module count(clk, reset, out);
output [3:0] out;
reg [3:0] out;
input clk,reset;
always @(posedge clk) begin
if (reset==0)
out<=0;
else
out<=out+1;
end
`probe(clk); // Sub-modules can also have `probe()
`probe(out);
endmodule
结果:
2.JOHNSON计数器n位计数2n个状态,相邻变化只有一位,同格雷码:
module top_module ();
reg clk=0;
always #5 clk = ~clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram
`probe(clk); // Probe signal "clk"
// A testbench
int k;
reg reset;
reg [3:0] out;
initial begin
reset=0;
#10 reset=1;
for(k=0;k<9;k++) begin
$display ("out=%b timr=%g",out,$time);
#10;
end
#10 $finish; // Quit the simulation
end
count inst1 (.clk(clk),.reset(reset),.out(out)); // Sub-modules work too.
endmodule
module count(clk, reset, out);
output [3:0] out;
reg [3:0] out;
input clk,reset;
always @(posedge clk) begin
if (reset==0)
out<=4'b0000;
else begin
if (out[0]==0)//第一位为0就推进1,第一位为1就推进0
out<={1'b1,out[3:1]};
else
out<={1'b0,out[3:1]};
end
end
`probe(clk); // Sub-modules can also have `probe()
`probe(out);
endmodule
结果(见其中变化过程):
3. 环形计数器,类似独热码,n位计数n个状态:
module top_module ();
reg clk=0;
always #5 clk = ~clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram
`probe(clk); // Probe signal "clk"
// A testbench
int k;
reg reset;
reg [3:0] out;
initial begin
reset=0;
#10 reset=1;
for(k=0;k<9;k++) begin
$display ("out=%b timr=%g",out,$time);
#10;
end
#10 $finish; // Quit the simulation
end
count inst1 (.clk(clk),.reset(reset),.out(out)); // Sub-modules work too.
endmodule
module count(clk, reset, out);
output [3:0] out;
reg [3:0] out;
input clk,reset;
always @(posedge clk) begin
if ((reset==0) | (out[0]==1))//or表示或门
out<=4'b1000;
else
out<={1'b0,out[3:1]};
end
`probe(clk); // Sub-modules can also have `probe()
`probe(out);
endmodule
输出: