FPGA学习笔记23 -- Johnson 计数器

module johnson(clk,clr,out); 

    input clk,clr; 

    output[3:0] out; 

    reg[3:0] out; 

    always @(posedge clk or posedge clr) 

        begin 

         if (clr)      out<= 4'h0; 

         else 

             begin     out<= out<< 1; 

                       out[0]<= ~out[3]; 

            end 

        end 

    endmodule 

module tb_johnson(); 

    reg clk,clr; 

    wire[3:0] out; 
 johnson u1(.clk(clk),.clr(clr),.out(out));
initial begin
clk<=1'b0;
clr<=1'b1;
#100 clr<=1'b0;
end
always #5 clk<=~clk;

    endmodule