HDLBits 刷题之我的代码（全）—（Circuits-Combinational Logic-Multiplexers）

#1

module top_module( 
    input a, b, sel,
    output out ); 
	assign out = sel ? b:a;
endmodule

#2

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
	assign out = sel ? b:a;
endmodule

#3

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always @(*) begin
        case(sel)
            'd0:out <= a;
            'd1:out <= b;
            'd2:out <= c;
            'd3:out <= d;
            'd4:out <= e;
            'd5:out <= f;
            'd6:out <= g;
            'd7:out <= h;
            'd8:out <= i;
            default : out <= 16'b1111111111111111;
        endcase
    end
endmodule

#4

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
 

endmodule

#5

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out[3] = in[(sel+1)*4-1];
    assign out[2] = in[(sel+1)*4-2];
    assign out[1] = in[(sel+1)*4-3];
    assign out[0] = in[(sel+1)*4-4];
endmodule