HDLBits 刷题之我的代码（全）—（Circuits-Combinational Logic-Karnaugh Map to Circuits）

#1

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    assign out = a | ((~a) & b) | ((~a) & c);
endmodule

#2

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = ((~b) & (~c)) | ((~a) & (~d)) | (b & c & d) | (a & (~b) & d);
endmodule

#3

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = a | ((~b) & c);
endmodule

#4

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = ((~a) & (~b) & c & (~d)) | (a & (~b) & (~c) & (~d)) | ((~a) & b & (~c) & (~d)) | ((~a) & (~b) & (~c) & d) | (a & b & (~c) & d) | ((~a) & b & c & d) | (a & (~b) & c & d) | (a & b & c & (~d));
endmodule

#5

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    assign out_sop = (c & d) | ((~a) & (~b) & c);
    assign out_pos = ~((~c) | (a & (~b)) | (b & (~d)));
endmodule

#6

module top_module (
    input [4:1] x, 
    output f );
    assign f = ((~x[1]) & x[3]) | (x[1] & x[2] & (~x[3]));
endmodule

#7

module top_module (
    input [4:1] x,
    output f
); 
    assign f = ((~x[1]) & x[3]) | (x[4] & x[2] & x[3]) | (~x[4] & ~x[2]);
	
endmodule

#8

在这里插入代码片

#9

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    always @(*) begin
        case({c,d})
            2'b0:
                mux_in = 4'b0100;
            2'b1:
                mux_in = 4'b0001;
            2'b11:
                mux_in = 4'b1001;
            default:
                mux_in = 4'b0101;
        endcase
    end
endmodule