HDLBits 刷题之我的代码（全）—（Verification:Reading Simulations-Finding bugs in codes）

#1

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );

    assign out = ({8{sel}} & a) | ({8{~sel}} & b);

endmodule

#2

module top_module (input a, input b, input c, output out);//
	wire out_reg;
    andgate inst1 ( out_reg,a, b, c,1,1);
	assign out = ~out_reg;
endmodule

#3

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //
	wire [7:0]x,y;
    mux2 mux0 ( sel[0],    a,    b, x );
    mux2 mux1 ( sel[0],    c,    d, y );
    mux2 mux2 ( sel[1], x, y,  out );

endmodule

#4

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output  result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase
    end
    assign result_is_zero = ~(|out) ? 1 : 0;
endmodule

#5

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid );//

    always @(*) begin
        valid = 0;
         out = 0;
        case (code)
            8'h45: begin
                out = 0;
                valid = 1;
            end
            8'h16: begin
                out = 1;
                valid = 1;
            end
            8'h1e: begin
                valid = 1; 
                out = 2;
            end
            8'h26: begin
                out = 3;
                valid = 1; 
            end
            8'h25: begin
                out = 4;
                valid = 1;
            end
            8'h2e: begin
                valid = 1;
                out = 5;
            end
            8'h36: begin
                valid = 1;
                out = 6;
            end
            8'h3d: begin
                valid = 1;
                out = 7;
            end
            8'h3e: begin
                valid = 1;
                out = 8;
            end
            8'h46: begin
                valid = 1;
                out = 9;
            end
            default: begin
                valid = 0;
                out = 0;
                end 
        endcase
    end
endmodule