[UVM]UVM Sequence item方法總結及使用案例

最新推荐文章于 2024-01-14 22:17:06 发布
最新推荐文章于 2024-01-14 22:17:06 发布
阅读量1.5k 收藏 13
点赞数 3
分类专栏： UVM
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/gsjthxy/article/details/105229602
版权

                                   UVM Sequence item Methods

 

1、create():

       The create method allocates a new object of the same type as this object and returns it via a base uvm_object handle.

2、print():

       The print method deep-prints this object’s properties in a format and manner governed by the given printer argument;

//-------------------------------------------------------------------------
//Simple TestBench to create and randomize sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item;
   
  initial begin
    //create method
    seq_item = mem_seq_item::type_id::create();
     
    //randomizing the seq_item
    seq_item.randomize();
     
    //printing the seq_item
    seq_item.print();  
  end 
endmodule

    Simulator Output:

---------------------------------------
Name Type Size Value
---------------------------------------
mem_seq_item mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
---------------------------------------

3、copy:

       The copy makes this object a copy of the specified object.

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item_0;
  mem_seq_item seq_item_1;
   
  initial begin
    //create method
    seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
    seq_item_1 = mem_seq_item::type_id::create("seq_item_1");
     
    seq_item_0.randomize(); //randomizing the seq_item  
    seq_item_0.print();     //printing the seq_item_0
     
    //copy method
    seq_item_1.copy(seq_item_0); //copy seq_item_0 to seq_item_1
    seq_item_1.print();          //printing the seq_item_1
     
  end 
endmodule

    Simulator Output:

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------

4、clone

       The clone method creates and returns an exact copy of this object. clone = create() + copy();

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item_0;
  mem_seq_item seq_item_1;
   
  initial begin
    //create method
    seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
     
    seq_item_0.randomize(); //randomizing the seq_item  
    seq_item_0.print();     //printing the seq_item_0
     
    //clone method
    $cast(seq_item_1,seq_item_0.clone()); //create seq_item_1 and copy seq_item_0 to seq_item_1
     
    //changing the seq_item_1 values will not reflect on seq_item_0 values.
    seq_item_1.addr  = 8;
    seq_item_1.wdata = 'h56;
    `uvm_info("","Printing seq_item_0", UVM_LOW)
    seq_item_0.print();          //printing the seq_item_0
    `uvm_info("","Printing seq_item_1", UVM_LOW)
    seq_item_1.print();          //printing the seq_item_1
     
    //Note:: name of seq_item_1 will be printed as seq_item_0, because there is no option to pass 
    //argument to
    //create method while calling the clone method.
  end 
endmodule

     Simulator Output:

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------
UVM_INFO testbench.sv(52) @ 0: reporter [] Printing seq_item_0
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------
UVM_INFO testbench.sv(54) @ 0: reporter [] Printing seq_item_1
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @338 
addr integral 4 'h8 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h56 
-------------------------------------

5、compare

       Deep compares members of this data object with those of the object provided in the RHS (right-hand side) argument, returning 1 on a match, 0 otherwise.

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item_0;
  mem_seq_item seq_item_1;
   
  initial begin
    //create method
    seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
    seq_item_1 = mem_seq_item::type_id::create("seq_item_1");   
     
    //---------------Mismatch Case------------------------------ 
    seq_item_0.randomize(); //randomizing the seq_item_0 
    seq_item_1.randomize(); //randomizing the seq_item_1 
     
    seq_item_0.print();     //printing the seq_item_0
    seq_item_1.print();     //printing the seq_item_1
     
    //compare method
    if(seq_item_0.compare(seq_item_1))
      `uvm_info("","seq_item_0 matching with seq_item_1", UVM_LOW)
    else
      `uvm_error("","seq_item_0 is not matching with seq_item_1")
     
    //---------------Matching Case------------------------------ 
    seq_item_1.copy(seq_item_0); //copy seq_item_0 to seq_item_1
    //compare method
    if(seq_item_0.compare(seq_item_1))
      `uvm_info("","seq_item_0 matching with seq_item_1", UVM_LOW)
    else
      `uvm_error("","seq_item_0 is not matching with seq_item_1")    
       
  end 
endmodule

    Simulator Output:

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h5 
wr_en integral 1 'h0 
rd_en integral 1 'h1 
wdata integral 8 'h33 
-------------------------------------
UVM_INFO @ 0: reporter [MISCMP] Miscompare for seq_item_0.addr: lhs = 'h4 : rhs = 'h5
UVM_INFO @ 0: reporter [MISCMP] 1 Miscompare(s) for object seq_item_1@338 vs. seq_item_0@334
UVM_ERROR testbench.sv(54) @ 0: reporter [] seq_item_0 is not matching with seq_item_1
UVM_INFO testbench.sv(59) @ 0: reporter [] seq_item_0 matching with seq_item_1

6、pack, pack_bytes, pack_ints

       The pack methods bitwise-concatenate this object’s properties into an array of bits, bytes, or ints.

(1)pack/unpack to/from array of bit type

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item_0;
  mem_seq_item seq_item_1;
  bit bit_packed_data[];
   
  initial begin
    //create method
    seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
    seq_item_1 = mem_seq_item::type_id::create("seq_item_1");
     
    //---------------------- PACK  ------------------------------ 
    seq_item_0.randomize(); //randomizing the seq_item_0
    seq_item_0.print();     //printing the seq_item_0
     
    seq_item_0.pack(bit_packed_data);    //pack method
    foreach(bit_packed_data[i])
      `uvm_info("PACK",$sformatf("bit_packed_data[%0d] = %b",i,bit_packed_data[i]), UVM_LOW)
       
    //---------------------- UNPACK ------------------------------
    `uvm_info("UNPACK","Before UnPack", UVM_LOW)
    seq_item_1.print();     //printing the seq_item_1
    seq_item_1.unpack(bit_packed_data);     //unpack method
    `uvm_info("UNPACK","After UnPack", UVM_LOW)
    seq_item_1.print();     //printing the seq_item_1
 
  end 
endmodule

    Simulator Output:

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[0] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[1] = 1
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[2] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[3] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[4] = 1
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[5] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[6] = 1
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[7] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[8] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[9] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[10] = 1
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[11] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[12] = 0
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] pack_data[13] = 0
UVM_INFO testbench.sv(54) @ 0: reporter [UNPACK] Before UnPack
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h0 
wr_en integral 1 'h0 
rd_en integral 1 'h0 
wdata integral 8 'h0 
-------------------------------------
UVM_INFO testbench.sv(57) @ 0: reporter [UNPACK] After UnPack
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------

(2)pack/unpack to/from array of byte type

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item_0;
  mem_seq_item seq_item_1;
  byte unsigned byte_packed_data[];
   
  initial begin
    //create method
    seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
    seq_item_1 = mem_seq_item::type_id::create("seq_item_1");
     
    //---------------------- PACK  ------------------------------ 
    seq_item_0.randomize(); //randomizing the seq_item_0
    seq_item_0.print();     //printing the seq_item_0
     
    seq_item_0.pack_bytes(byte_packed_data);    //pack method
     
    foreach(byte_packed_data[i])
      `uvm_info("PACK",$sformatf("byte_packed_data[%0d] = %b",i,byte_packed_data[i]), UVM_LOW)
       
    //---------------------- UNPACK ------------------------------
    `uvm_info("UNPACK","Before UnPack", UVM_LOW)
    seq_item_1.print();     //printing the seq_item_1
     
    seq_item_1.unpack_bytes(byte_packed_data);     //unpack method
     
    `uvm_info("UNPACK","After UnPack", UVM_LOW)
    seq_item_1.print();     //printing the seq_item_1
 
  end 
endmodule

    Simulator Output:

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------

UVM_INFO testbench.sv(51) @ 0: reporter [PACK] byte_packed_data[0] = 01001010
UVM_INFO testbench.sv(51) @ 0: reporter [PACK] byte_packed_data[1] = 00100000
UVM_INFO testbench.sv(54) @ 0: reporter [UNPACK] Before UnPack

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h0 
wr_en integral 1 'h0 
rd_en integral 1 'h0 
wdata integral 8 'h0 
-------------------------------------

UVM_INFO testbench.sv(57) @ 0: reporter [UNPACK] After UnPack

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------

(3)pack/unpack to/from array of int type

//-------------------------------------------------------------------------
//Simple TestBench to access sequence item
//-------------------------------------------------------------------------
module seq_item_tb;
   
  //instance
  mem_seq_item seq_item_0;
  mem_seq_item seq_item_1;
  int unsigned int_packed_data[];
   
  initial begin
    //create method
    seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
    seq_item_1 = mem_seq_item::type_id::create("seq_item_1");
     
    //---------------------- PACK  ------------------------------ 
    seq_item_0.randomize(); //randomizing the seq_item_0
    seq_item_0.print();     //printing the seq_item_0
     
    seq_item_0.pack_ints(int_packed_data);    //pack method
     
    foreach(int_packed_data[i])
      `uvm_info("PACK",$sformatf("int_packed_data[%0d] = %b",i,int_packed_data[i]), UVM_LOW)
       
    //---------------------- UNPACK ------------------------------
    `uvm_info("UNPACK","Before UnPack", UVM_LOW)
    seq_item_1.print();     //printing the seq_item_1
     
    seq_item_1.unpack_ints(int_packed_data);     //unpack method
     
    `uvm_info("UNPACK","After UnPack", UVM_LOW)
    seq_item_1.print();     //printing the seq_item_1
 
  end 
endmodule

    Simulator Output: 

-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_0 mem_seq_item - @334 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------
UVM_INFO testbench.sv(52) @ 0: reporter [PACK] int_packed_data[0] = 01001010001000000000000000000000
UVM_INFO testbench.sv(55) @ 0: reporter [UNPACK] Before UnPack
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h0 
wr_en integral 1 'h0 
rd_en integral 1 'h0 
wdata integral 8 'h0 
-------------------------------------
UVM_INFO testbench.sv(60) @ 0: reporter [UNPACK] After UnPack
-------------------------------------
Name Type Size Value
-------------------------------------
seq_item_1 mem_seq_item - @338 
addr integral 4 'h4 
wr_en integral 1 'h1 
rd_en integral 1 'h0 
wdata integral 8 'h88 
-------------------------------------

 

元直数字电路验证
关注
  • 3
    点赞
  • 踩
  • 13
    收藏
    觉得还不错? 一键收藏
  • 打赏
    打赏
  • 0
    评论
专栏目录
UVM——sequence & item
weixin_42482170的博客
03-23 1117
此处sequence泛指uvm_sequence_item类，item泛指uvm_sequence_item类。 sequence用来实现激励生成和场景控制；item实现对激励所需要的具体数据和控制要求。 sequence item介绍 item基于uvm_object类，具备UVM核心基类所必要的数据操作方法，如copy()，clone()，compare()，record()等。通常将它们划分为以下类： - 控制类。如总线协议上的读写类型、数据长度、传送模式等。 - 负载类。一般指数据总线上的数据包。
(16)UVM sequence和item
数字IC小白的日常修炼
11-17 1256
UVM sequence和item 文章目录UVM sequence和item一、概述二、sequence item介绍 一、概述 无论是自驾item，穿过sequencer交通站通往终点driver，还是坐上sequence大巴，一路沿途观光，一路沿途观光，最终跟随导游 停靠到风景点driver。 在介绍如何驾驶item和sequence，遵守什么交规，最终可以有序穿过sequencer抵达driver之前，有必要首先认识sequence与item之间的关系。 这里的sequence指的是uvm_seq
UVM实战-UVM验证方法学.pdf
07-15
IC芯片验证测试平台的搭建，UVM测试平台环境搭建以及验证方法学
UVM基础学习.ppt
02-13
UVM基础学习PPT，讲述了UVM的基础内容，包括UVM框架、agent、sequence、phase等基础内容。
UVM简易环境生成脚本
06-06
systemverilog，UVM验证环境自动生成器，主要是利用tcl脚本一键生成，可以用于windows下modelsim仿真工程，只供参考
SV及UVM接口应用_systemverilog_dpi-c_uvm验证_UVM_UVMDPI_
09-29
我们本节谈DPI的应用将就着更简单直观的实际场景，来谈一谈如何满足那些习惯于写C测试的“老测试员”们，使得他们可以在C环境下写C测试用例，而无需关注与底层验证环境是否由UVM实现还是实际硬件去执行C的代码。
基于UVM的AHB总线SRAM控制器设计验证平台设计
08-11
1、设计基于AHB总线的SRAM读写控制器：根据AHB总线输入hsize与haddr自动选择块与片选，在原有基础上，增加了8位数据与16位数据深度，即当hsize选择8位数据传输时，数据深度为8*8k=2^16，当选择16位时，数据深度为4*8k=2^15，当数据为32位时，深度与原有一样为2*8k=2^14。 2、设计基于UVM的验证框架：设计两级sequencer与sequence分别控制读写、设计两个case分别为边写边读与写满读空。
UVM::sequence_item的定义
sxlwzl的专栏
08-27 1950
import uvm_pkg::*; class packet extends uvm_sequence_item; rand int addr; rand int data; rand int len; rand int crc; function new (string name = "packet"); super.new(name); this.crc.rand_
[UVM]UVM Sequence item
元直的博客
03-31 937
UVM Sequence item The sequence-item is written by extending the uvm_sequence_item, uvm_sequence_item inherits from the uvm_object via the uvm_transaction cl...
（8）UVM Sequence和Item
数字IC攻城狮
11-21 613
（8）UVM Sequence和Item概述itemitem示例 概述 在介绍如何使用item和 sequence，可以有序穿过 sequencer抵达 driver之前，有必要首先认识 sequence与item之间的关系。 这里的 sequence指的是 uvm_ sequence类，而item指的是uvm_sequence_item类，我们简称其为 sequence和item。对于激励生成和场景控制，是由 sequence来编织的，而对于激励所需要的具体数据和控制要求，则是从item的成员数据得来的。
uvm1.2源码
01-21
最新的uvm1.2源代码，深入学习uvm验证最佳的资料。
UVM1.1应用指南及源代码分析
02-02
本书前半部分介绍了UVM的应用,后半部分分析了UVM的源代码,详细讲解了UVM的factory机制,sequence机制,config机制,objection机制,phase机制及register model。希望能够跟大家一起学习交流讨论UVM。如果有问题请联系...
UVM的copy及clone和print
最新发布
m0_71354184的博客
01-14 610
UVM的print copy clone
Sequencer和Sequence
qq_39794062的博客
03-02 1410
一、sequence和item发送实例 class bus_trans extends uvm_sequence_item; rand int data; `uvm_object_utils_begin(bus_trans) `uvm_field_int(data, UVM_ALL_ON) `uvm_object_utils_end ... endclass class child_seq extends uvm_sequence; `uvm_object_utils(child_seq);
Sequence和Item
qq_39794062的博客
03-01 1691
一、概述 sequence指的是uvm_sequence类，而item指的是uvm_sequence_item类。 对于激励生成和场景控制，是由sequence来编织的，而对于激励所需要的具体数据和控制要求，则是从item的成员数据得到的。 二、Sequence Item介绍 item是基于uvm_object类，这表明了它具备UVM核心基类所必要的数据操作方法，例如copy()、clone()、compare()、record()。item根据数据成员的类型，将划分为： 控制类。例如总线协议上的读写
python自动化产生uvm组件 — 产生item(1)
qq_40260113的博客
07-18 722
item是一个重复劳动的的待吗任务，所以希望写一个python脚本解决这个问题，下面是是学习的python写的第一版代码，后面持续完善！！！ import os import time import sys import xlrd import numpy as np def print_do_copy(): template.append("\nfunction void "+str(classname)+"::do_copy( uvm_object rhs)") template.a
UVM--sequence和item 序列通信
创芯人--fly的博客
04-25 2141
本小节主要介绍了sequence和item的关系，以及sequence中常见的几种类型。更多详细内容之后结合实验项目补充。
UVM学习整理——UVM通信（sequence）
lizhao_yang_的博客
11-28 4120
五、sequence UVM的sequence机制最大的作用就是将test case和testbench分离开来。 对一个项目而言，testbench是相对稳定的框架，而针对各个module要有不同的测试内容，所以具体的test case 的差异非常大。在UVM中， test和sequence类总是成对出现，实现了testbench和具体的test case的结合。test类中可以针对具体的测试内容对testbench做一些差异化配置，在sequence类中则是实现test case的具体...
[VCS]merge coverage --- vdb merge
热门推荐
元直的博客
03-12 1万+
一、記錄一些常用的VCS Command merge coverage：urg -full64 -metric line+tgl+cond+fsm+assert+branch -warn none -dbname <merge_coverage_name>.vdb -dir simv.vdb -elfile <el_filename.el> 注意：其中-dir之後的第...
uvm sequence item 设计模式
09-06
总结来说，UVM Sequence Item设计模式提供了一种有效的方法来抽象和建模待验证对象，使得验证工作更加高效、灵活和可维护。它是UVM验证框架中不可或缺的一部分，对于复杂的设计验证工程具有重要的意义。

“相关推荐”对你有帮助么？

  • 非常没帮助
  • 没帮助
  • 一般
  • 有帮助
  • 非常有帮助
提交
评论
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包

打赏作者

元直数字电路验证

你的鼓励将是我创作的最大动力

¥1 ¥2 ¥4 ¥6 ¥10 ¥20
扫码支付：¥1
获取中
扫码支付

您的余额不足，请更换扫码支付或充值

打赏作者

实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值